xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/spl.c (revision afc6362a095eee3963bbc5ca82b4ed0aedc184aa) 
1 /*
2  * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <boot_rkimg.h>
9 #include <debug_uart.h>
10 #include <dm.h>
11 #include <key.h>
12 #include <led.h>
13 #include <misc.h>
14 #include <ram.h>
15 #include <spl.h>
16 #include <optee_include/OpteeClientInterface.h>
17 #include <power/fuel_gauge.h>
18 #include <asm/arch/bootrom.h>
19 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
20 #include <asm/arch/rk_atags.h>
21 #endif
22 #include <asm/arch/sdram.h>
23 #include <asm/arch/boot_mode.h>
24 #include <asm/arch-rockchip/sys_proto.h>
25 #include <asm/io.h>
26 #include <asm/arch/param.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 void board_return_to_bootrom(void)
31 {
32 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
33 }
34 
35 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
36 };
37 
38 const char *board_spl_was_booted_from(void)
39 {
40 	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
41 	const char *bootdevice_ofpath = NULL;
42 
43 	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
44 		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
45 
46 	if (bootdevice_ofpath)
47 		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
48 		      __func__, bootdevice_brom_id, bootdevice_ofpath);
49 	else
50 		debug("%s: failed to resolve brom_bootdevice_id %x\n",
51 		      __func__, bootdevice_brom_id);
52 
53 	return bootdevice_ofpath;
54 }
55 
56 u32 spl_boot_device(void)
57 {
58 	u32 boot_device = BOOT_DEVICE_MMC1;
59 
60 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
61 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
62 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
63 	return BOOT_DEVICE_SPI;
64 #endif
65 	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
66 		return BOOT_DEVICE_BOOTROM;
67 
68 	return boot_device;
69 }
70 
71 u32 spl_boot_mode(const u32 boot_device)
72 {
73 	return MMCSD_MODE_RAW;
74 }
75 
76 __weak void rockchip_stimer_init(void)
77 {
78 	/* If Timer already enabled, don't re-init it */
79 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
80 	if ( reg & 0x1 )
81 		return;
82 #ifndef CONFIG_ARM64
83 	asm volatile("mcr p15, 0, %0, c14, c0, 0"
84 		     : : "r"(COUNTER_FREQUENCY));
85 #endif
86 	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
87 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
88 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
89 	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
90 }
91 
92 __weak int arch_cpu_init(void)
93 {
94 	return 0;
95 }
96 
97 __weak int rk_board_init_f(void)
98 {
99 	return 0;
100 }
101 
102 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
103 void udelay(unsigned long usec)
104 {
105 	__udelay(usec);
106 }
107 
108 void hang(void)
109 {
110 	bootstage_error(BOOTSTAGE_ID_NEED_RESET);
111 	for (;;)
112 		;
113 }
114 
115 /**
116  * memset - Fill a region of memory with the given value
117  * @s: Pointer to the start of the area.
118  * @c: The byte to fill the area with
119  * @count: The size of the area.
120  *
121  * Do not use memset() to access IO space, use memset_io() instead.
122  */
123 void *memset(void *s, int c, size_t count)
124 {
125 	unsigned long *sl = (unsigned long *)s;
126 	char *s8;
127 
128 #if !CONFIG_IS_ENABLED(TINY_MEMSET)
129 	unsigned long cl = 0;
130 	int i;
131 
132 	/* do it one word at a time (32 bits or 64 bits) while possible */
133 	if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
134 		for (i = 0; i < sizeof(*sl); i++) {
135 			cl <<= 8;
136 			cl |= c & 0xff;
137 		}
138 		while (count >= sizeof(*sl)) {
139 			*sl++ = cl;
140 			count -= sizeof(*sl);
141 		}
142 	}
143 #endif /* fill 8 bits at a time */
144 	s8 = (char *)sl;
145 	while (count--)
146 		*s8++ = c;
147 
148 	return s;
149 }
150 #endif
151 
152 void board_init_f(ulong dummy)
153 {
154 #ifdef CONFIG_SPL_FRAMEWORK
155 	int ret;
156 #if !defined(CONFIG_SUPPORT_TPL)
157 	struct udevice *dev;
158 #endif
159 #endif
160 	gd->flags = dummy;
161 	rockchip_stimer_init();
162 #define EARLY_UART
163 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
164 	/*
165 	 * Debug UART can be used from here if required:
166 	 *
167 	 * debug_uart_init();
168 	 * printch('a');
169 	 * printhex8(0x1234);
170 	 * printascii("string");
171 	 */
172 	if (!gd->serial.using_pre_serial &&
173 	    !(gd->flags & GD_FLG_DISABLE_CONSOLE))
174 		debug_uart_init();
175 	printascii("U-Boot SPL board init");
176 #endif
177 	gd->sys_start_tick = get_ticks();
178 #ifdef CONFIG_SPL_FRAMEWORK
179 	ret = spl_early_init();
180 	if (ret) {
181 		printf("spl_early_init() failed: %d\n", ret);
182 		hang();
183 	}
184 #if !defined(CONFIG_SUPPORT_TPL)
185 	debug("\nspl:init dram\n");
186 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
187 	if (ret) {
188 		printf("DRAM init failed: %d\n", ret);
189 		return;
190 	}
191 #endif
192 	preloader_console_init();
193 #else
194 	/* Some SoCs like rk3036 does not use any frame work */
195 	sdram_init();
196 #endif
197 
198 	arch_cpu_init();
199 	rk_board_init_f();
200 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
201 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
202 #endif
203 
204 }
205 
206 #ifdef CONFIG_SPL_LOAD_FIT
207 int board_fit_config_name_match(const char *name)
208 {
209 	/* Just empty function now - can't decide what to choose */
210 	debug("%s: %s\n", __func__, name);
211 
212 	return 0;
213 }
214 #endif
215 
216 int board_init_f_boot_flags(void)
217 {
218 	int boot_flags = 0;
219 
220 #ifdef CONFIG_PSTORE
221        param_parse_pstore();
222 #endif
223 
224 	/* pre-loader serial */
225 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
226     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
227 	struct tag *t;
228 
229 
230 	t = atags_get_tag(ATAG_SERIAL);
231 	if (t) {
232 		gd->serial.using_pre_serial = 1;
233 		gd->serial.enable = t->u.serial.enable;
234 		gd->serial.baudrate = t->u.serial.baudrate;
235 		gd->serial.addr = t->u.serial.addr;
236 		gd->serial.id = t->u.serial.id;
237 		gd->baudrate = t->u.serial.baudrate;
238 		if (!t->u.serial.enable)
239 			boot_flags |= GD_FLG_DISABLE_CONSOLE;
240 		debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
241 		      t->u.serial.enable, (u32)t->u.serial.addr,
242 		      t->u.serial.baudrate, t->u.serial.id);
243 	} else
244 #endif
245 	{
246 		gd->baudrate = CONFIG_BAUDRATE;
247 		gd->serial.baudrate = CONFIG_BAUDRATE;
248 		gd->serial.addr = CONFIG_DEBUG_UART_BASE;
249 	}
250 
251 	/* The highest priority to turn off (override) console */
252 #if defined(CONFIG_DISABLE_CONSOLE)
253 	boot_flags |= GD_FLG_DISABLE_CONSOLE;
254 #endif
255 
256 	return boot_flags;
257 }
258 
259 #ifdef CONFIG_SPL_BOARD_INIT
260 __weak int rk_spl_board_init(void)
261 {
262 	return 0;
263 }
264 
265 static int setup_led(void)
266 {
267 #ifdef CONFIG_SPL_LED
268 	struct udevice *dev;
269 	char *led_name;
270 	int ret;
271 
272 	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
273 	if (!led_name)
274 		return 0;
275 	ret = led_get_by_label(led_name, &dev);
276 	if (ret) {
277 		debug("%s: get=%d\n", __func__, ret);
278 		return ret;
279 	}
280 	ret = led_set_state(dev, LEDST_ON);
281 	if (ret)
282 		return ret;
283 #endif
284 
285 	return 0;
286 }
287 
288 void spl_board_init(void)
289 {
290 	int ret;
291 
292 	ret = setup_led();
293 
294 	if (ret) {
295 		debug("LED ret=%d\n", ret);
296 		hang();
297 	}
298 
299 	rk_spl_board_init();
300 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
301 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
302 #endif
303 	return;
304 }
305 #endif
306 
307 void spl_perform_fixups(struct spl_image_info *spl_image)
308 {
309 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
310 	atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
311 #endif
312 	return;
313 }
314 
315 #ifdef CONFIG_SPL_KERNEL_BOOT
316 static int spl_rockchip_dnl_key_pressed(void)
317 {
318 #if defined(CONFIG_SPL_INPUT)
319 	return key_read(KEY_VOLUMEUP);
320 #else
321 	return 0;
322 #endif
323 }
324 
325 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
326 bool spl_is_low_power(void)
327 {
328 	struct udevice *dev;
329 	int ret, voltage;
330 
331 	ret = uclass_get_device(UCLASS_FG, 0, &dev);
332 	if (ret) {
333 		debug("Get charge display failed, ret=%d\n", ret);
334 		return false;
335 	}
336 
337 	voltage = fuel_gauge_get_voltage(dev);
338 	if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD)
339 		return false;
340 
341 	return true;
342 }
343 #endif
344 
345 void spl_next_stage(struct spl_image_info *spl)
346 {
347 	uint32_t reg_boot_mode;
348 
349 	if (spl_rockchip_dnl_key_pressed()) {
350 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
351 		return;
352 	}
353 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
354 	if (spl_is_low_power()) {
355 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
356 		return;
357 	}
358 #endif
359 
360 	reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
361 	switch (reg_boot_mode) {
362 	case BOOT_COLD:
363 	case BOOT_PANIC:
364 	case BOOT_WATCHDOG:
365 	case BOOT_NORMAL:
366 	case BOOT_RECOVERY:
367 		spl->next_stage = SPL_NEXT_STAGE_KERNEL;
368 		break;
369 	default:
370 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
371 	}
372 }
373 #endif
374 
375 #ifdef CONFIG_SPL_KERNEL_BOOT
376 const char *spl_kernel_partition(struct spl_image_info *spl,
377 				 struct spl_load_info *info)
378 {
379 	struct bootloader_message *bmsg = NULL;
380 	u32 boot_mode;
381 	int ret, cnt;
382 	u32 sector = 0;
383 
384 #ifdef CONFIG_SPL_LIBDISK_SUPPORT
385 	disk_partition_t part_info;
386 
387 	ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
388 	if (ret >= 0)
389 		sector = part_info.start;
390 #else
391 	sector = CONFIG_SPL_MISC_SECTOR;
392 #endif
393 	if (sector) {
394 		cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
395 		bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
396 		ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
397 				 cnt, bmsg);
398 		if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
399 			free(bmsg);
400 			return PART_RECOVERY;
401 		} else {
402 			free(bmsg);
403 		}
404 	}
405 
406 	boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
407 
408 	return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
409 }
410 #endif
411 
412 void spl_hang_reset(void)
413 {
414 	printf("# Reset the board to bootrom #\n");
415 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
416 	/* reset is available after dm setup */
417 	if (gd->flags & GD_FLG_SPL_EARLY_INIT) {
418 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
419 		do_reset(NULL, 0, 0, NULL);
420 	}
421 #endif
422 }
423 
424 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
425 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
426 {
427 	int ret = 0;
428 
429 	*otp_index = 0;
430 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
431 	struct udevice *dev;
432 	u32 index, i, otp_version;
433 	u32 bit_count;
434 
435 	dev = misc_otp_get_device(OTP_S);
436 	if (!dev)
437 		return -ENODEV;
438 
439 	otp_version = 0;
440 	for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
441 		if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
442 		    &index,
443 		    4)) {
444 			printf("Can't read rollback index\n");
445 			return -EIO;
446 		}
447 
448 		bit_count = fls(index);
449 		otp_version += bit_count;
450 	}
451 	*otp_index = otp_version;
452 #endif
453 
454 	return ret;
455 }
456 
457 static int fit_write_otp_rollback_index(u32 fit_index)
458 {
459 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
460 	struct udevice *dev;
461 	u32 index, i, otp_index;
462 
463 	if (!fit_index)
464 		return 0;
465 
466 	if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
467 		return -EINVAL;
468 
469 	dev = misc_otp_get_device(OTP_S);
470 	if (!dev)
471 		return -ENODEV;
472 
473 	if (fit_read_otp_rollback_index(fit_index, &otp_index))
474 		return -EIO;
475 
476 	if (otp_index < fit_index) {
477 		/* Write new SW version to otp */
478 		for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
479 			/*
480 			 * If fit_index is equal to 0, then execute 0xffffffff >> 32.
481 			 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is
482 			 * actually be "0xffffffff >> 0".
483 			 */
484 			if (!fit_index)
485 				break;
486 			/* convert to base-1 representation */
487 			index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
488 				min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
489 			fit_index -= min(fit_index,
490 					  (u32)OTP_ALL_ONES_NUM_BITS);
491 			if (index) {
492 				if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
493 				    &index,
494 				    4)) {
495 					printf("Can't write rollback index\n");
496 					return -EIO;
497 				}
498 			}
499 		}
500 	}
501 #endif
502 
503 	return 0;
504 }
505 #endif
506 
507 int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
508 {
509 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
510 	int ret;
511 
512 	ret = fit_write_otp_rollback_index(gd->rollback_index);
513 	if (ret) {
514 		panic("Failed to write fit rollback index %d, ret=%d",
515 		      gd->rollback_index, ret);
516 	}
517 #endif
518 
519 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
520 	misc_decompress_cleanup();
521 #endif
522 	return 0;
523 }
524