1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <boot_rkimg.h> 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <key.h> 12 #include <led.h> 13 #include <misc.h> 14 #include <ram.h> 15 #include <spl.h> 16 #include <optee_include/OpteeClientInterface.h> 17 #include <power/fuel_gauge.h> 18 #include <asm/arch/bootrom.h> 19 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 20 #include <asm/arch/rk_atags.h> 21 #endif 22 #include <asm/arch/sdram.h> 23 #include <asm/arch/boot_mode.h> 24 #include <asm/arch-rockchip/sys_proto.h> 25 #include <asm/io.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 void board_return_to_bootrom(void) 30 { 31 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 32 } 33 34 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 35 }; 36 37 const char *board_spl_was_booted_from(void) 38 { 39 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 40 const char *bootdevice_ofpath = NULL; 41 42 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 43 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 44 45 if (bootdevice_ofpath) 46 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 47 __func__, bootdevice_brom_id, bootdevice_ofpath); 48 else 49 debug("%s: failed to resolve brom_bootdevice_id %x\n", 50 __func__, bootdevice_brom_id); 51 52 return bootdevice_ofpath; 53 } 54 55 u32 spl_boot_device(void) 56 { 57 u32 boot_device = BOOT_DEVICE_MMC1; 58 59 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 60 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 61 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 62 return BOOT_DEVICE_SPI; 63 #endif 64 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 65 return BOOT_DEVICE_BOOTROM; 66 67 return boot_device; 68 } 69 70 u32 spl_boot_mode(const u32 boot_device) 71 { 72 return MMCSD_MODE_RAW; 73 } 74 75 __weak void rockchip_stimer_init(void) 76 { 77 /* If Timer already enabled, don't re-init it */ 78 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 79 if ( reg & 0x1 ) 80 return; 81 #ifndef CONFIG_ARM64 82 asm volatile("mcr p15, 0, %0, c14, c0, 0" 83 : : "r"(COUNTER_FREQUENCY)); 84 #endif 85 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 86 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 87 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 88 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 89 } 90 91 __weak int arch_cpu_init(void) 92 { 93 return 0; 94 } 95 96 __weak int rk_board_init_f(void) 97 { 98 return 0; 99 } 100 101 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 102 void udelay(unsigned long usec) 103 { 104 __udelay(usec); 105 } 106 107 void hang(void) 108 { 109 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 110 for (;;) 111 ; 112 } 113 114 /** 115 * memset - Fill a region of memory with the given value 116 * @s: Pointer to the start of the area. 117 * @c: The byte to fill the area with 118 * @count: The size of the area. 119 * 120 * Do not use memset() to access IO space, use memset_io() instead. 121 */ 122 void *memset(void *s, int c, size_t count) 123 { 124 unsigned long *sl = (unsigned long *)s; 125 char *s8; 126 127 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 128 unsigned long cl = 0; 129 int i; 130 131 /* do it one word at a time (32 bits or 64 bits) while possible */ 132 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 133 for (i = 0; i < sizeof(*sl); i++) { 134 cl <<= 8; 135 cl |= c & 0xff; 136 } 137 while (count >= sizeof(*sl)) { 138 *sl++ = cl; 139 count -= sizeof(*sl); 140 } 141 } 142 #endif /* fill 8 bits at a time */ 143 s8 = (char *)sl; 144 while (count--) 145 *s8++ = c; 146 147 return s; 148 } 149 #endif 150 151 void board_init_f(ulong dummy) 152 { 153 #ifdef CONFIG_SPL_FRAMEWORK 154 int ret; 155 #if !defined(CONFIG_SUPPORT_TPL) 156 struct udevice *dev; 157 #endif 158 #endif 159 160 rockchip_stimer_init(); 161 #define EARLY_UART 162 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 163 /* 164 * Debug UART can be used from here if required: 165 * 166 * debug_uart_init(); 167 * printch('a'); 168 * printhex8(0x1234); 169 * printascii("string"); 170 */ 171 if (!gd->serial.using_pre_serial && 172 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 173 debug_uart_init(); 174 printascii("U-Boot SPL board init"); 175 #endif 176 gd->sys_start_tick = get_ticks(); 177 #ifdef CONFIG_SPL_FRAMEWORK 178 ret = spl_early_init(); 179 if (ret) { 180 printf("spl_early_init() failed: %d\n", ret); 181 hang(); 182 } 183 #if !defined(CONFIG_SUPPORT_TPL) 184 debug("\nspl:init dram\n"); 185 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 186 if (ret) { 187 printf("DRAM init failed: %d\n", ret); 188 return; 189 } 190 #endif 191 preloader_console_init(); 192 #else 193 /* Some SoCs like rk3036 does not use any frame work */ 194 sdram_init(); 195 #endif 196 197 arch_cpu_init(); 198 rk_board_init_f(); 199 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 200 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 201 #endif 202 203 } 204 205 #ifdef CONFIG_SPL_LOAD_FIT 206 int board_fit_config_name_match(const char *name) 207 { 208 /* Just empty function now - can't decide what to choose */ 209 debug("%s: %s\n", __func__, name); 210 211 return 0; 212 } 213 #endif 214 215 int board_init_f_boot_flags(void) 216 { 217 int boot_flags = 0; 218 219 /* pre-loader serial */ 220 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 221 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 222 struct tag *t; 223 224 225 t = atags_get_tag(ATAG_SERIAL); 226 if (t) { 227 gd->serial.using_pre_serial = 1; 228 gd->serial.enable = t->u.serial.enable; 229 gd->serial.baudrate = t->u.serial.baudrate; 230 gd->serial.addr = t->u.serial.addr; 231 gd->serial.id = t->u.serial.id; 232 gd->baudrate = t->u.serial.baudrate; 233 if (!t->u.serial.enable) 234 boot_flags |= GD_FLG_DISABLE_CONSOLE; 235 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 236 t->u.serial.enable, (u32)t->u.serial.addr, 237 t->u.serial.baudrate, t->u.serial.id); 238 } else 239 #endif 240 { 241 gd->baudrate = CONFIG_BAUDRATE; 242 gd->serial.baudrate = CONFIG_BAUDRATE; 243 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 244 } 245 246 /* The highest priority to turn off (override) console */ 247 #if defined(CONFIG_DISABLE_CONSOLE) 248 boot_flags |= GD_FLG_DISABLE_CONSOLE; 249 #endif 250 251 return boot_flags; 252 } 253 254 #ifdef CONFIG_SPL_BOARD_INIT 255 __weak int rk_spl_board_init(void) 256 { 257 return 0; 258 } 259 260 static int setup_led(void) 261 { 262 #ifdef CONFIG_SPL_LED 263 struct udevice *dev; 264 char *led_name; 265 int ret; 266 267 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 268 if (!led_name) 269 return 0; 270 ret = led_get_by_label(led_name, &dev); 271 if (ret) { 272 debug("%s: get=%d\n", __func__, ret); 273 return ret; 274 } 275 ret = led_set_state(dev, LEDST_ON); 276 if (ret) 277 return ret; 278 #endif 279 280 return 0; 281 } 282 283 void spl_board_init(void) 284 { 285 int ret; 286 287 ret = setup_led(); 288 289 if (ret) { 290 debug("LED ret=%d\n", ret); 291 hang(); 292 } 293 294 rk_spl_board_init(); 295 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 296 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 297 #endif 298 return; 299 } 300 #endif 301 302 void spl_perform_fixups(struct spl_image_info *spl_image) 303 { 304 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 305 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 306 #endif 307 return; 308 } 309 310 #ifdef CONFIG_SPL_KERNEL_BOOT 311 static int spl_rockchip_dnl_key_pressed(void) 312 { 313 #if defined(CONFIG_SPL_INPUT) 314 return key_read(KEY_VOLUMEUP); 315 #else 316 return 0; 317 #endif 318 } 319 320 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 321 bool spl_is_low_power(void) 322 { 323 struct udevice *dev; 324 int ret, voltage; 325 326 ret = uclass_get_device(UCLASS_FG, 0, &dev); 327 if (ret) { 328 debug("Get charge display failed, ret=%d\n", ret); 329 return false; 330 } 331 332 voltage = fuel_gauge_get_voltage(dev); 333 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 334 return false; 335 336 return true; 337 } 338 #endif 339 340 void spl_next_stage(struct spl_image_info *spl) 341 { 342 uint32_t reg_boot_mode; 343 344 if (spl_rockchip_dnl_key_pressed()) { 345 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 346 return; 347 } 348 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 349 if (spl_is_low_power()) { 350 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 351 return; 352 } 353 #endif 354 355 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 356 switch (reg_boot_mode) { 357 case BOOT_COLD: 358 case BOOT_PANIC: 359 case BOOT_WATCHDOG: 360 case BOOT_NORMAL: 361 case BOOT_RECOVERY: 362 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 363 break; 364 default: 365 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 366 } 367 } 368 #endif 369 370 #ifdef CONFIG_SPL_KERNEL_BOOT 371 const char *spl_kernel_partition(struct spl_image_info *spl, 372 struct spl_load_info *info) 373 { 374 struct bootloader_message *bmsg = NULL; 375 u32 boot_mode; 376 int ret, cnt; 377 u32 sector = 0; 378 379 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 380 disk_partition_t part_info; 381 382 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 383 if (ret >= 0) 384 sector = part_info.start; 385 #else 386 sector = CONFIG_SPL_MISC_SECTOR; 387 #endif 388 if (sector) { 389 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 390 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 391 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 392 cnt, bmsg); 393 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 394 free(bmsg); 395 return PART_RECOVERY; 396 } else { 397 free(bmsg); 398 } 399 } 400 401 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 402 403 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 404 } 405 #endif 406 407 void spl_hang_reset(void) 408 { 409 printf("# Reset the board to bootrom #\n"); 410 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 411 /* reset is available after dm setup */ 412 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 413 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 414 do_reset(NULL, 0, 0, NULL); 415 } 416 #endif 417 } 418 419 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 420 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 421 { 422 int ret = 0; 423 424 *otp_index = 0; 425 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) || defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V1) 426 struct udevice *dev; 427 u32 index, i, otp_version; 428 u32 bit_count; 429 430 dev = misc_otp_get_device(OTP_S); 431 if (!dev) 432 return -ENODEV; 433 434 otp_version = 0; 435 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 436 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 437 &index, 438 4)) { 439 printf("Can't read rollback index\n"); 440 return -EIO; 441 } 442 443 bit_count = fls(index); 444 otp_version += bit_count; 445 } 446 *otp_index = otp_version; 447 #endif 448 449 return ret; 450 } 451 452 static int fit_write_otp_rollback_index(u32 fit_index) 453 { 454 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) || defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V1) 455 struct udevice *dev; 456 u32 index, i, otp_index; 457 458 if (!fit_index) 459 return 0; 460 461 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 462 return -EINVAL; 463 464 dev = misc_otp_get_device(OTP_S); 465 if (!dev) 466 return -ENODEV; 467 468 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 469 return -EIO; 470 471 if (otp_index < fit_index) { 472 /* Write new SW version to otp */ 473 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 474 /* 475 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 476 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 477 * actually be "0xffffffff >> 0". 478 */ 479 if (!fit_index) 480 break; 481 /* convert to base-1 representation */ 482 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 483 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 484 fit_index -= min(fit_index, 485 (u32)OTP_ALL_ONES_NUM_BITS); 486 if (index) { 487 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 488 &index, 489 4)) { 490 printf("Can't write rollback index\n"); 491 return -EIO; 492 } 493 } 494 } 495 } 496 #endif 497 498 return 0; 499 } 500 #endif 501 502 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 503 { 504 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 505 int ret; 506 507 ret = fit_write_otp_rollback_index(gd->rollback_index); 508 if (ret) { 509 panic("Failed to write fit rollback index %d, ret=%d", 510 gd->rollback_index, ret); 511 } 512 #endif 513 514 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 515 misc_decompress_cleanup(); 516 #endif 517 return 0; 518 } 519