xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/spl.c (revision 70ad550d6f37befbc82a8e5e7c7753be83ff08b1) 
1 /*
2  * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <boot_rkimg.h>
9 #include <debug_uart.h>
10 #include <dm.h>
11 #include <key.h>
12 #include <led.h>
13 #include <misc.h>
14 #include <ram.h>
15 #include <spl.h>
16 #include <optee_include/OpteeClientInterface.h>
17 #include <power/fuel_gauge.h>
18 #include <asm/arch/bootrom.h>
19 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
20 #include <asm/arch/rk_atags.h>
21 #endif
22 #include <asm/arch/pcie_ep_boot.h>
23 #include <asm/arch/sdram.h>
24 #include <asm/arch/boot_mode.h>
25 #include <asm/arch-rockchip/sys_proto.h>
26 #include <asm/io.h>
27 #include <asm/arch/param.h>
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 void board_return_to_bootrom(void)
32 {
33 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
34 }
35 
36 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
37 };
38 
39 const char *board_spl_was_booted_from(void)
40 {
41 	u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
42 	const char *bootdevice_ofpath = NULL;
43 
44 	if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
45 		bootdevice_ofpath = boot_devices[bootdevice_brom_id];
46 
47 	if (bootdevice_ofpath)
48 		debug("%s: brom_bootdevice_id %x maps to '%s'\n",
49 		      __func__, bootdevice_brom_id, bootdevice_ofpath);
50 	else
51 		debug("%s: failed to resolve brom_bootdevice_id %x\n",
52 		      __func__, bootdevice_brom_id);
53 
54 	return bootdevice_ofpath;
55 }
56 
57 u32 spl_boot_device(void)
58 {
59 	u32 boot_device = BOOT_DEVICE_MMC1;
60 
61 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
62 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
63 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
64 	return BOOT_DEVICE_SPI;
65 #endif
66 	if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
67 		return BOOT_DEVICE_BOOTROM;
68 
69 	return boot_device;
70 }
71 
72 u32 spl_boot_mode(const u32 boot_device)
73 {
74 	return MMCSD_MODE_RAW;
75 }
76 
77 __weak void rockchip_stimer_init(void)
78 {
79 	/* If Timer already enabled, don't re-init it */
80 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
81 	if ( reg & 0x1 )
82 		return;
83 #ifndef CONFIG_ARM64
84 	asm volatile("mcr p15, 0, %0, c14, c0, 0"
85 		     : : "r"(COUNTER_FREQUENCY));
86 #endif
87 	writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
88 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
89 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
90 	writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
91 }
92 
93 __weak int arch_cpu_init(void)
94 {
95 	return 0;
96 }
97 
98 __weak int rk_board_init_f(void)
99 {
100 	return 0;
101 }
102 
103 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
104 void udelay(unsigned long usec)
105 {
106 	__udelay(usec);
107 }
108 
109 void hang(void)
110 {
111 	bootstage_error(BOOTSTAGE_ID_NEED_RESET);
112 	for (;;)
113 		;
114 }
115 
116 /**
117  * memset - Fill a region of memory with the given value
118  * @s: Pointer to the start of the area.
119  * @c: The byte to fill the area with
120  * @count: The size of the area.
121  *
122  * Do not use memset() to access IO space, use memset_io() instead.
123  */
124 void *memset(void *s, int c, size_t count)
125 {
126 	unsigned long *sl = (unsigned long *)s;
127 	char *s8;
128 
129 #if !CONFIG_IS_ENABLED(TINY_MEMSET)
130 	unsigned long cl = 0;
131 	int i;
132 
133 	/* do it one word at a time (32 bits or 64 bits) while possible */
134 	if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
135 		for (i = 0; i < sizeof(*sl); i++) {
136 			cl <<= 8;
137 			cl |= c & 0xff;
138 		}
139 		while (count >= sizeof(*sl)) {
140 			*sl++ = cl;
141 			count -= sizeof(*sl);
142 		}
143 	}
144 #endif /* fill 8 bits at a time */
145 	s8 = (char *)sl;
146 	while (count--)
147 		*s8++ = c;
148 
149 	return s;
150 }
151 #endif
152 
153 void board_init_f(ulong dummy)
154 {
155 #ifdef CONFIG_SPL_FRAMEWORK
156 	int ret;
157 #if !defined(CONFIG_SUPPORT_TPL)
158 	struct udevice *dev;
159 #endif
160 #endif
161 	gd->flags = dummy;
162 	rockchip_stimer_init();
163 #define EARLY_UART
164 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
165 	/*
166 	 * Debug UART can be used from here if required:
167 	 *
168 	 * debug_uart_init();
169 	 * printch('a');
170 	 * printhex8(0x1234);
171 	 * printascii("string");
172 	 */
173 	if (!gd->serial.using_pre_serial &&
174 	    !(gd->flags & GD_FLG_DISABLE_CONSOLE))
175 		debug_uart_init();
176 	printascii("U-Boot SPL board init");
177 #endif
178 	gd->sys_start_tick = get_ticks();
179 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT
180 	rockchip_pcie_ep_init();
181 #endif
182 #ifdef CONFIG_SPL_FRAMEWORK
183 	ret = spl_early_init();
184 	if (ret) {
185 		printf("spl_early_init() failed: %d\n", ret);
186 		hang();
187 	}
188 #if !defined(CONFIG_SUPPORT_TPL)
189 	debug("\nspl:init dram\n");
190 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
191 	if (ret) {
192 		printf("DRAM init failed: %d\n", ret);
193 		return;
194 	}
195 #endif
196 	preloader_console_init();
197 #else
198 	/* Some SoCs like rk3036 does not use any frame work */
199 	sdram_init();
200 #endif
201 
202 	arch_cpu_init();
203 	rk_board_init_f();
204 #ifdef CONFIG_SPL_RAM_DEVICE
205 	rockchip_pcie_ep_get_firmware();
206 #endif
207 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
208 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
209 #endif
210 
211 }
212 
213 #ifdef CONFIG_SPL_LOAD_FIT
214 int board_fit_config_name_match(const char *name)
215 {
216 	/* Just empty function now - can't decide what to choose */
217 	debug("%s: %s\n", __func__, name);
218 
219 	return 0;
220 }
221 #endif
222 
223 int board_init_f_boot_flags(void)
224 {
225 	int boot_flags = 0;
226 
227 #ifdef CONFIG_FPGA_ROCKCHIP
228 	arch_fpga_init();
229 #endif
230 #ifdef CONFIG_PSTORE
231 	param_parse_pstore();
232 #endif
233 	/* pre-loader serial */
234 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
235     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
236 	struct tag *t;
237 
238 	t = atags_get_tag(ATAG_SERIAL);
239 	if (t) {
240 		gd->serial.using_pre_serial = 1;
241 		gd->serial.enable = t->u.serial.enable;
242 		gd->serial.baudrate = t->u.serial.baudrate;
243 		gd->serial.addr = t->u.serial.addr;
244 		gd->serial.id = t->u.serial.id;
245 		gd->baudrate = t->u.serial.baudrate;
246 		if (!t->u.serial.enable)
247 			boot_flags |= GD_FLG_DISABLE_CONSOLE;
248 		debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
249 		      t->u.serial.enable, (u32)t->u.serial.addr,
250 		      t->u.serial.baudrate, t->u.serial.id);
251 	} else
252 #endif
253 	{
254 		gd->baudrate = CONFIG_BAUDRATE;
255 		gd->serial.baudrate = CONFIG_BAUDRATE;
256 		gd->serial.addr = CONFIG_DEBUG_UART_BASE;
257 	}
258 
259 	/* The highest priority to turn off (override) console */
260 #if defined(CONFIG_DISABLE_CONSOLE)
261 	boot_flags |= GD_FLG_DISABLE_CONSOLE;
262 #endif
263 
264 	return boot_flags;
265 }
266 
267 #ifdef CONFIG_SPL_BOARD_INIT
268 __weak int rk_spl_board_init(void)
269 {
270 	return 0;
271 }
272 
273 static int setup_led(void)
274 {
275 #ifdef CONFIG_SPL_LED
276 	struct udevice *dev;
277 	char *led_name;
278 	int ret;
279 
280 	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
281 	if (!led_name)
282 		return 0;
283 	ret = led_get_by_label(led_name, &dev);
284 	if (ret) {
285 		debug("%s: get=%d\n", __func__, ret);
286 		return ret;
287 	}
288 	ret = led_set_state(dev, LEDST_ON);
289 	if (ret)
290 		return ret;
291 #endif
292 
293 	return 0;
294 }
295 
296 void spl_board_init(void)
297 {
298 	int ret;
299 
300 	ret = setup_led();
301 
302 	if (ret) {
303 		debug("LED ret=%d\n", ret);
304 		hang();
305 	}
306 
307 	rk_spl_board_init();
308 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
309 	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
310 #endif
311 	return;
312 }
313 #endif
314 
315 void spl_perform_fixups(struct spl_image_info *spl_image)
316 {
317 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
318 	atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
319 #endif
320 	return;
321 }
322 
323 #ifdef CONFIG_SPL_KERNEL_BOOT
324 static int spl_rockchip_dnl_key_pressed(void)
325 {
326 #if defined(CONFIG_SPL_INPUT)
327 	return key_read(KEY_VOLUMEUP);
328 #else
329 	return 0;
330 #endif
331 }
332 
333 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
334 bool spl_is_low_power(void)
335 {
336 	struct udevice *dev;
337 	int ret, voltage;
338 
339 	ret = uclass_get_device(UCLASS_FG, 0, &dev);
340 	if (ret) {
341 		debug("Get charge display failed, ret=%d\n", ret);
342 		return false;
343 	}
344 
345 	voltage = fuel_gauge_get_voltage(dev);
346 	if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD)
347 		return false;
348 
349 	return true;
350 }
351 #endif
352 
353 void spl_next_stage(struct spl_image_info *spl)
354 {
355 	uint32_t reg_boot_mode;
356 
357 	if (spl_rockchip_dnl_key_pressed()) {
358 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
359 		return;
360 	}
361 #ifdef CONFIG_SPL_DM_FUEL_GAUGE
362 	if (spl_is_low_power()) {
363 		spl->next_stage = SPL_NEXT_STAGE_UBOOT;
364 		return;
365 	}
366 #endif
367 
368 	reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
369 	switch (reg_boot_mode) {
370 	case BOOT_COLD:
371 	case BOOT_PANIC:
372 	case BOOT_WATCHDOG:
373 	case BOOT_NORMAL:
374 	case BOOT_RECOVERY:
375 		spl->next_stage = SPL_NEXT_STAGE_KERNEL;
376 		break;
377 	default:
378 		if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG)
379 			spl->next_stage = SPL_NEXT_STAGE_KERNEL;
380 		else
381 			spl->next_stage = SPL_NEXT_STAGE_UBOOT;
382 	}
383 }
384 #endif
385 
386 #ifdef CONFIG_SPL_KERNEL_BOOT
387 const char *spl_kernel_partition(struct spl_image_info *spl,
388 				 struct spl_load_info *info)
389 {
390 	struct bootloader_message *bmsg = NULL;
391 	u32 boot_mode;
392 	int ret, cnt;
393 	u32 sector = 0;
394 
395 #ifdef CONFIG_SPL_LIBDISK_SUPPORT
396 	disk_partition_t part_info;
397 
398 	ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
399 	if (ret >= 0)
400 		sector = part_info.start;
401 #else
402 	sector = CONFIG_SPL_MISC_SECTOR;
403 #endif
404 	if (sector) {
405 		cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
406 		bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
407 		ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
408 				 cnt, bmsg);
409 		if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
410 			free(bmsg);
411 			return PART_RECOVERY;
412 		} else {
413 			free(bmsg);
414 		}
415 	}
416 
417 	boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
418 
419 	return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
420 }
421 #endif
422 
423 void spl_hang_reset(void)
424 {
425 	printf("# Reset the board to bootrom #\n");
426 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
427 	/* reset is available after dm setup */
428 	if (gd->flags & GD_FLG_SPL_EARLY_INIT) {
429 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
430 		do_reset(NULL, 0, 0, NULL);
431 	}
432 #endif
433 }
434 
435 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
436 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
437 {
438 	int ret = 0;
439 
440 	*otp_index = 0;
441 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
442 	struct udevice *dev;
443 	u32 index, i, otp_version;
444 	u32 bit_count;
445 
446 	dev = misc_otp_get_device(OTP_S);
447 	if (!dev)
448 		return -ENODEV;
449 
450 	otp_version = 0;
451 	for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
452 		if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
453 		    &index,
454 		    4)) {
455 			printf("Can't read rollback index\n");
456 			return -EIO;
457 		}
458 
459 		bit_count = fls(index);
460 		otp_version += bit_count;
461 	}
462 	*otp_index = otp_version;
463 #endif
464 
465 	return ret;
466 }
467 
468 static int fit_write_otp_rollback_index(u32 fit_index)
469 {
470 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
471 	struct udevice *dev;
472 	u32 index, i, otp_index;
473 
474 	if (!fit_index)
475 		return 0;
476 
477 	if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
478 		return -EINVAL;
479 
480 	dev = misc_otp_get_device(OTP_S);
481 	if (!dev)
482 		return -ENODEV;
483 
484 	if (fit_read_otp_rollback_index(fit_index, &otp_index))
485 		return -EIO;
486 
487 	if (otp_index < fit_index) {
488 		/* Write new SW version to otp */
489 		for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
490 			/*
491 			 * If fit_index is equal to 0, then execute 0xffffffff >> 32.
492 			 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is
493 			 * actually be "0xffffffff >> 0".
494 			 */
495 			if (!fit_index)
496 				break;
497 			/* convert to base-1 representation */
498 			index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
499 				min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
500 			fit_index -= min(fit_index,
501 					  (u32)OTP_ALL_ONES_NUM_BITS);
502 			if (index) {
503 				if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
504 				    &index,
505 				    4)) {
506 					printf("Can't write rollback index\n");
507 					return -EIO;
508 				}
509 			}
510 		}
511 	}
512 #endif
513 
514 	return 0;
515 }
516 #endif
517 
518 int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
519 {
520 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
521 	int ret;
522 
523 	ret = fit_write_otp_rollback_index(gd->rollback_index);
524 	if (ret) {
525 		panic("Failed to write fit rollback index %d, ret=%d",
526 		      gd->rollback_index, ret);
527 	}
528 #endif
529 
530 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
531 	misc_decompress_cleanup();
532 #endif
533 	return 0;
534 }
535