1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <boot_rkimg.h> 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <key.h> 12 #include <led.h> 13 #include <misc.h> 14 #include <ram.h> 15 #include <spl.h> 16 #include <optee_include/OpteeClientInterface.h> 17 #include <power/fuel_gauge.h> 18 #include <asm/arch/bootrom.h> 19 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 20 #include <asm/arch/rk_atags.h> 21 #endif 22 #include <asm/arch/pcie_ep_boot.h> 23 #include <asm/arch/sdram.h> 24 #include <asm/arch/boot_mode.h> 25 #include <asm/arch-rockchip/sys_proto.h> 26 #include <asm/io.h> 27 #include <asm/arch/param.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 void board_return_to_bootrom(void) 32 { 33 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 34 } 35 36 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 37 }; 38 39 const char *board_spl_was_booted_from(void) 40 { 41 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 42 const char *bootdevice_ofpath = NULL; 43 44 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 45 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 46 47 if (bootdevice_ofpath) 48 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 49 __func__, bootdevice_brom_id, bootdevice_ofpath); 50 else 51 debug("%s: failed to resolve brom_bootdevice_id %x\n", 52 __func__, bootdevice_brom_id); 53 54 return bootdevice_ofpath; 55 } 56 57 u32 spl_boot_device(void) 58 { 59 u32 boot_device = BOOT_DEVICE_MMC1; 60 61 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 62 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 63 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 64 return BOOT_DEVICE_SPI; 65 #endif 66 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 67 return BOOT_DEVICE_BOOTROM; 68 69 return boot_device; 70 } 71 72 u32 spl_boot_mode(const u32 boot_device) 73 { 74 return MMCSD_MODE_RAW; 75 } 76 77 __weak void rockchip_stimer_init(void) 78 { 79 /* If Timer already enabled, don't re-init it */ 80 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 81 if ( reg & 0x1 ) 82 return; 83 #ifndef CONFIG_ARM64 84 asm volatile("mcr p15, 0, %0, c14, c0, 0" 85 : : "r"(COUNTER_FREQUENCY)); 86 #endif 87 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 88 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 89 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 90 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 91 } 92 93 __weak int arch_cpu_init(void) 94 { 95 return 0; 96 } 97 98 __weak int rk_board_init_f(void) 99 { 100 return 0; 101 } 102 103 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 104 void udelay(unsigned long usec) 105 { 106 __udelay(usec); 107 } 108 109 void hang(void) 110 { 111 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 112 for (;;) 113 ; 114 } 115 116 /** 117 * memset - Fill a region of memory with the given value 118 * @s: Pointer to the start of the area. 119 * @c: The byte to fill the area with 120 * @count: The size of the area. 121 * 122 * Do not use memset() to access IO space, use memset_io() instead. 123 */ 124 void *memset(void *s, int c, size_t count) 125 { 126 unsigned long *sl = (unsigned long *)s; 127 char *s8; 128 129 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 130 unsigned long cl = 0; 131 int i; 132 133 /* do it one word at a time (32 bits or 64 bits) while possible */ 134 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 135 for (i = 0; i < sizeof(*sl); i++) { 136 cl <<= 8; 137 cl |= c & 0xff; 138 } 139 while (count >= sizeof(*sl)) { 140 *sl++ = cl; 141 count -= sizeof(*sl); 142 } 143 } 144 #endif /* fill 8 bits at a time */ 145 s8 = (char *)sl; 146 while (count--) 147 *s8++ = c; 148 149 return s; 150 } 151 #endif 152 153 #ifdef CONFIG_SPL_DM_RESET 154 static void brom_download(void) 155 { 156 if (debug_uart_tstc() && debug_uart_getc() == 0x02) { 157 printf("ctrl+b: Bootrom download!\n"); 158 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 do_reset(NULL, 0, 0, NULL); 160 } 161 } 162 #endif 163 164 void board_init_f(ulong dummy) 165 { 166 #ifdef CONFIG_SPL_FRAMEWORK 167 int ret; 168 #if !defined(CONFIG_SUPPORT_TPL) 169 struct udevice *dev; 170 #endif 171 #endif 172 gd->flags = dummy; 173 rockchip_stimer_init(); 174 #define EARLY_UART 175 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 176 /* 177 * Debug UART can be used from here if required: 178 * 179 * debug_uart_init(); 180 * printch('a'); 181 * printhex8(0x1234); 182 * printascii("string"); 183 */ 184 if (!gd->serial.using_pre_serial && 185 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 186 debug_uart_init(); 187 printascii("U-Boot SPL board init"); 188 #endif 189 gd->sys_start_tick = get_ticks(); 190 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 191 rockchip_pcie_ep_init(); 192 #endif 193 #ifdef CONFIG_SPL_FRAMEWORK 194 ret = spl_early_init(); 195 if (ret) { 196 printf("spl_early_init() failed: %d\n", ret); 197 hang(); 198 } 199 #if !defined(CONFIG_SUPPORT_TPL) 200 debug("\nspl:init dram\n"); 201 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 202 if (ret) { 203 printf("DRAM init failed: %d\n", ret); 204 return; 205 } 206 #endif 207 preloader_console_init(); 208 #else 209 /* Some SoCs like rk3036 does not use any frame work */ 210 sdram_init(); 211 #endif 212 #ifdef CONFIG_SPL_DM_RESET 213 brom_download(); 214 #endif 215 arch_cpu_init(); 216 rk_board_init_f(); 217 #ifdef CONFIG_SPL_RAM_DEVICE 218 rockchip_pcie_ep_get_firmware(); 219 #endif 220 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 221 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 222 #endif 223 224 } 225 226 #ifdef CONFIG_SPL_LOAD_FIT 227 int board_fit_config_name_match(const char *name) 228 { 229 /* Just empty function now - can't decide what to choose */ 230 debug("%s: %s\n", __func__, name); 231 232 return 0; 233 } 234 #endif 235 236 int board_init_f_boot_flags(void) 237 { 238 int boot_flags = 0; 239 240 #ifdef CONFIG_FPGA_ROCKCHIP 241 arch_fpga_init(); 242 #endif 243 #ifdef CONFIG_PSTORE 244 param_parse_pstore(); 245 #endif 246 /* pre-loader serial */ 247 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 248 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 249 struct tag *t; 250 251 t = atags_get_tag(ATAG_SERIAL); 252 if (t) { 253 gd->serial.using_pre_serial = 1; 254 gd->serial.enable = t->u.serial.enable; 255 gd->serial.baudrate = t->u.serial.baudrate; 256 gd->serial.addr = t->u.serial.addr; 257 gd->serial.id = t->u.serial.id; 258 gd->baudrate = t->u.serial.baudrate; 259 if (!t->u.serial.enable) 260 boot_flags |= GD_FLG_DISABLE_CONSOLE; 261 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 262 t->u.serial.enable, (u32)t->u.serial.addr, 263 t->u.serial.baudrate, t->u.serial.id); 264 } else 265 #endif 266 { 267 gd->baudrate = CONFIG_BAUDRATE; 268 gd->serial.baudrate = CONFIG_BAUDRATE; 269 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 270 } 271 272 /* The highest priority to turn off (override) console */ 273 #if defined(CONFIG_DISABLE_CONSOLE) 274 boot_flags |= GD_FLG_DISABLE_CONSOLE; 275 #endif 276 277 return boot_flags; 278 } 279 280 #ifdef CONFIG_SPL_BOARD_INIT 281 __weak int rk_spl_board_init(void) 282 { 283 return 0; 284 } 285 286 static int setup_led(void) 287 { 288 #ifdef CONFIG_SPL_LED 289 struct udevice *dev; 290 char *led_name; 291 int ret; 292 293 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 294 if (!led_name) 295 return 0; 296 ret = led_get_by_label(led_name, &dev); 297 if (ret) { 298 debug("%s: get=%d\n", __func__, ret); 299 return ret; 300 } 301 ret = led_set_state(dev, LEDST_ON); 302 if (ret) 303 return ret; 304 #endif 305 306 return 0; 307 } 308 309 void spl_board_init(void) 310 { 311 int ret; 312 313 ret = setup_led(); 314 315 if (ret) { 316 debug("LED ret=%d\n", ret); 317 hang(); 318 } 319 320 rk_spl_board_init(); 321 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 322 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 323 #endif 324 return; 325 } 326 #endif 327 328 void spl_perform_fixups(struct spl_image_info *spl_image) 329 { 330 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 331 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 332 #endif 333 return; 334 } 335 336 #ifdef CONFIG_SPL_KERNEL_BOOT 337 static int spl_rockchip_dnl_key_pressed(void) 338 { 339 #if defined(CONFIG_SPL_INPUT) 340 return key_read(KEY_VOLUMEUP); 341 #else 342 return 0; 343 #endif 344 } 345 346 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 347 bool spl_is_low_power(void) 348 { 349 struct udevice *dev; 350 int ret, voltage; 351 352 ret = uclass_get_device(UCLASS_FG, 0, &dev); 353 if (ret) { 354 debug("Get charge display failed, ret=%d\n", ret); 355 return false; 356 } 357 358 voltage = fuel_gauge_get_voltage(dev); 359 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 360 return false; 361 362 return true; 363 } 364 #endif 365 366 void spl_next_stage(struct spl_image_info *spl) 367 { 368 uint32_t reg_boot_mode; 369 370 if (spl_rockchip_dnl_key_pressed()) { 371 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 372 return; 373 } 374 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 375 if (spl_is_low_power()) { 376 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 377 return; 378 } 379 #endif 380 381 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 382 switch (reg_boot_mode) { 383 case BOOT_COLD: 384 case BOOT_PANIC: 385 case BOOT_WATCHDOG: 386 case BOOT_NORMAL: 387 case BOOT_RECOVERY: 388 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 389 break; 390 default: 391 if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG) 392 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 393 else 394 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 395 } 396 } 397 #endif 398 399 #ifdef CONFIG_SPL_KERNEL_BOOT 400 const char *spl_kernel_partition(struct spl_image_info *spl, 401 struct spl_load_info *info) 402 { 403 struct bootloader_message *bmsg = NULL; 404 u32 boot_mode; 405 int ret, cnt; 406 u32 sector = 0; 407 408 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 409 disk_partition_t part_info; 410 411 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 412 if (ret >= 0) 413 sector = part_info.start; 414 #else 415 sector = CONFIG_SPL_MISC_SECTOR; 416 #endif 417 if (sector) { 418 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 419 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 420 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 421 cnt, bmsg); 422 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 423 free(bmsg); 424 return PART_RECOVERY; 425 } else { 426 free(bmsg); 427 } 428 } 429 430 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 431 432 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 433 } 434 #endif 435 436 void spl_hang_reset(void) 437 { 438 printf("# Reset the board to bootrom #\n"); 439 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 440 /* reset is available after dm setup */ 441 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 442 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 443 do_reset(NULL, 0, 0, NULL); 444 } 445 #endif 446 } 447 448 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 449 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 450 { 451 int ret = 0; 452 453 *otp_index = 0; 454 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 455 struct udevice *dev; 456 u32 index, i, otp_version; 457 u32 bit_count; 458 459 dev = misc_otp_get_device(OTP_S); 460 if (!dev) 461 return -ENODEV; 462 463 otp_version = 0; 464 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 465 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 466 &index, 467 4)) { 468 printf("Can't read rollback index\n"); 469 return -EIO; 470 } 471 472 bit_count = fls(index); 473 otp_version += bit_count; 474 } 475 *otp_index = otp_version; 476 #endif 477 478 return ret; 479 } 480 481 static int fit_write_otp_rollback_index(u32 fit_index) 482 { 483 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 484 struct udevice *dev; 485 u32 index, i, otp_index; 486 487 if (!fit_index) 488 return 0; 489 490 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 491 return -EINVAL; 492 493 dev = misc_otp_get_device(OTP_S); 494 if (!dev) 495 return -ENODEV; 496 497 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 498 return -EIO; 499 500 if (otp_index < fit_index) { 501 /* Write new SW version to otp */ 502 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 503 /* 504 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 505 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 506 * actually be "0xffffffff >> 0". 507 */ 508 if (!fit_index) 509 break; 510 /* convert to base-1 representation */ 511 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 512 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 513 fit_index -= min(fit_index, 514 (u32)OTP_ALL_ONES_NUM_BITS); 515 if (index) { 516 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 517 &index, 518 4)) { 519 printf("Can't write rollback index\n"); 520 return -EIO; 521 } 522 } 523 } 524 } 525 #endif 526 527 return 0; 528 } 529 #endif 530 531 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 532 { 533 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 534 int ret; 535 536 ret = fit_write_otp_rollback_index(gd->rollback_index); 537 if (ret) { 538 panic("Failed to write fit rollback index %d, ret=%d", 539 gd->rollback_index, ret); 540 } 541 #endif 542 543 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 544 misc_decompress_cleanup(); 545 #endif 546 return 0; 547 } 548