1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 #include <asm/arch/rk_hwid.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 void board_return_to_bootrom(void) 34 { 35 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 36 } 37 38 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 39 }; 40 41 const char *board_spl_was_booted_from(void) 42 { 43 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 44 const char *bootdevice_ofpath = NULL; 45 46 if ((bootdevice_brom_id & BROM_DOWNLOAD_MASK) == BROM_DOWNLOAD_MASK) 47 bootdevice_brom_id = BROM_BOOTSOURCE_USB; 48 49 bootdevice_brom_id = bootdevice_brom_id & BROM_BOOTSOURCE_MASK; 50 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 51 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 52 53 if (bootdevice_ofpath) 54 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 55 __func__, bootdevice_brom_id, bootdevice_ofpath); 56 else 57 debug("%s: failed to resolve brom_bootdevice_id %x\n", 58 __func__, bootdevice_brom_id); 59 60 return bootdevice_ofpath; 61 } 62 63 u32 spl_boot_device(void) 64 { 65 u32 boot_device = BOOT_DEVICE_MMC1; 66 67 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 68 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 69 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 70 return BOOT_DEVICE_SPI; 71 #endif 72 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 73 return BOOT_DEVICE_BOOTROM; 74 75 return boot_device; 76 } 77 78 u32 spl_boot_mode(const u32 boot_device) 79 { 80 return MMCSD_MODE_RAW; 81 } 82 83 __weak void rockchip_stimer_init(void) 84 { 85 /* If Timer already enabled, don't re-init it */ 86 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 87 if ( reg & 0x1 ) 88 return; 89 #ifndef CONFIG_ARM64 90 asm volatile("mcr p15, 0, %0, c14, c0, 0" 91 : : "r"(COUNTER_FREQUENCY)); 92 #endif 93 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 94 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 95 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 96 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 97 } 98 99 __weak int arch_cpu_init(void) 100 { 101 return 0; 102 } 103 104 __weak int rk_board_init_f(void) 105 { 106 return 0; 107 } 108 109 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 110 void udelay(unsigned long usec) 111 { 112 __udelay(usec); 113 } 114 115 void hang(void) 116 { 117 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 118 for (;;) 119 ; 120 } 121 122 /** 123 * memset - Fill a region of memory with the given value 124 * @s: Pointer to the start of the area. 125 * @c: The byte to fill the area with 126 * @count: The size of the area. 127 * 128 * Do not use memset() to access IO space, use memset_io() instead. 129 */ 130 void *memset(void *s, int c, size_t count) 131 { 132 unsigned long *sl = (unsigned long *)s; 133 char *s8; 134 135 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 136 unsigned long cl = 0; 137 int i; 138 139 /* do it one word at a time (32 bits or 64 bits) while possible */ 140 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 141 for (i = 0; i < sizeof(*sl); i++) { 142 cl <<= 8; 143 cl |= c & 0xff; 144 } 145 while (count >= sizeof(*sl)) { 146 *sl++ = cl; 147 count -= sizeof(*sl); 148 } 149 } 150 #endif /* fill 8 bits at a time */ 151 s8 = (char *)sl; 152 while (count--) 153 *s8++ = c; 154 155 return s; 156 } 157 #endif 158 159 #ifdef CONFIG_SPL_DM_RESET 160 static void brom_download(void) 161 { 162 if (gd->console_evt == 0x02) { 163 printf("ctrl+b: Bootrom download!\n"); 164 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 165 do_reset(NULL, 0, 0, NULL); 166 } 167 } 168 #endif 169 170 static void spl_hotkey_init(void) 171 { 172 /* If disable console, skip getting uart reg */ 173 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE) 174 return; 175 if (!gd->have_console) 176 return; 177 178 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */ 179 #ifdef CONFIG_SPL_FRAMEWORK 180 if (serial_tstc()) { 181 gd->console_evt = serial_getc(); 182 #else 183 if (debug_uart_tstc()) { 184 gd->console_evt = debug_uart_getc(); 185 #endif 186 if (gd->console_evt <= 0x1a) /* 'z' */ 187 printf("SPL Hotkey: ctrl+%c\n", 188 gd->console_evt + 'a' - 1); 189 } 190 191 return; 192 } 193 194 void board_init_f(ulong dummy) 195 { 196 #ifdef CONFIG_SPL_FRAMEWORK 197 int ret; 198 #if !defined(CONFIG_SUPPORT_TPL) 199 struct udevice *dev; 200 #endif 201 #endif 202 gd->flags = dummy; 203 rockchip_stimer_init(); 204 #define EARLY_UART 205 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 206 /* 207 * Debug UART can be used from here if required: 208 * 209 * debug_uart_init(); 210 * printch('a'); 211 * printhex8(0x1234); 212 * printascii("string"); 213 */ 214 if (!gd->serial.using_pre_serial && 215 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 216 debug_uart_init(); 217 printascii("U-Boot SPL board init"); 218 #endif 219 gd->sys_start_tick = get_ticks(); 220 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 221 rockchip_pcie_ep_init(); 222 #endif 223 #ifdef CONFIG_SPL_FRAMEWORK 224 ret = spl_early_init(); 225 if (ret) { 226 printf("spl_early_init() failed: %d\n", ret); 227 hang(); 228 } 229 #if !defined(CONFIG_SUPPORT_TPL) 230 debug("\nspl:init dram\n"); 231 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 232 if (ret) { 233 printf("DRAM init failed: %d\n", ret); 234 return; 235 } 236 #endif 237 preloader_console_init(); 238 #else 239 /* Some SoCs like rk3036 does not use any frame work */ 240 sdram_init(); 241 #endif 242 /* Get hotkey and store in gd */ 243 spl_hotkey_init(); 244 #ifdef CONFIG_SPL_DM_RESET 245 brom_download(); 246 #endif 247 arch_cpu_init(); 248 rk_board_init_f(); 249 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT) 250 rockchip_pcie_ep_get_firmware(); 251 #endif 252 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 253 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 254 #endif 255 256 } 257 258 #ifdef CONFIG_SPL_LOAD_FIT 259 int board_fit_config_name_match(const char *name) 260 { 261 /* Just empty function now - can't decide what to choose */ 262 debug("%s: %s\n", __func__, name); 263 264 return 0; 265 } 266 #endif 267 268 int board_init_f_boot_flags(void) 269 { 270 int boot_flags = 0; 271 272 #if CONFIG_IS_ENABLED(FPGA_ROCKCHIP) 273 arch_fpga_init(); 274 #endif 275 #ifdef CONFIG_PSTORE 276 param_parse_pstore(); 277 #endif 278 /* pre-loader serial */ 279 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 280 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 281 struct tag *t; 282 283 t = atags_get_tag(ATAG_SERIAL); 284 if (t) { 285 gd->serial.using_pre_serial = 1; 286 gd->serial.enable = t->u.serial.enable; 287 gd->serial.baudrate = t->u.serial.baudrate; 288 gd->serial.addr = t->u.serial.addr; 289 gd->serial.id = t->u.serial.id; 290 gd->baudrate = t->u.serial.baudrate; 291 if (!t->u.serial.enable) 292 boot_flags |= GD_FLG_DISABLE_CONSOLE; 293 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 294 t->u.serial.enable, (u32)t->u.serial.addr, 295 t->u.serial.baudrate, t->u.serial.id); 296 } else 297 #endif 298 { 299 gd->baudrate = CONFIG_BAUDRATE; 300 gd->serial.baudrate = CONFIG_BAUDRATE; 301 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 302 } 303 304 /* The highest priority to turn off (override) console */ 305 #if defined(CONFIG_DISABLE_CONSOLE) 306 boot_flags |= GD_FLG_DISABLE_CONSOLE; 307 #endif 308 309 return boot_flags; 310 } 311 312 #ifdef CONFIG_SPL_BOARD_INIT 313 __weak int rk_spl_board_init(void) 314 { 315 return 0; 316 } 317 318 static int setup_led(void) 319 { 320 #ifdef CONFIG_SPL_LED 321 struct udevice *dev; 322 char *led_name; 323 int ret; 324 325 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 326 if (!led_name) 327 return 0; 328 ret = led_get_by_label(led_name, &dev); 329 if (ret) { 330 debug("%s: get=%d\n", __func__, ret); 331 return ret; 332 } 333 ret = led_set_state(dev, LEDST_ON); 334 if (ret) 335 return ret; 336 #endif 337 338 return 0; 339 } 340 341 void spl_board_init(void) 342 { 343 int ret; 344 345 ret = setup_led(); 346 347 if (ret) { 348 debug("LED ret=%d\n", ret); 349 hang(); 350 } 351 352 rk_spl_board_init(); 353 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 354 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 355 #endif 356 return; 357 } 358 #endif 359 360 #ifdef CONFIG_SPL_KERNEL_BOOT 361 static int spl_rockchip_dnl_key_pressed(void) 362 { 363 #if defined(CONFIG_SPL_INPUT) 364 return key_read(KEY_VOLUMEUP); 365 #else 366 return 0; 367 #endif 368 } 369 370 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 371 bool spl_is_low_power(void) 372 { 373 struct udevice *dev; 374 int ret, voltage; 375 376 ret = uclass_get_device(UCLASS_FG, 0, &dev); 377 if (ret) { 378 debug("Get charge display failed, ret=%d\n", ret); 379 return false; 380 } 381 382 voltage = fuel_gauge_get_voltage(dev); 383 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 384 return false; 385 386 return true; 387 } 388 #endif 389 390 void spl_next_stage(struct spl_image_info *spl) 391 { 392 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Other" }; 393 uint32_t reg_boot_mode; 394 int i = 0; 395 396 if (spl_rockchip_dnl_key_pressed()) { 397 i = 0; 398 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 399 goto out; 400 } 401 402 if (gd->console_evt == 0x03) { 403 i = 1; 404 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 405 goto out; 406 } 407 408 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 409 if (spl_is_low_power()) { 410 i = 2; 411 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 412 goto out; 413 } 414 #endif 415 416 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 417 switch (reg_boot_mode) { 418 case BOOT_LOADER: 419 case BOOT_FASTBOOT: 420 case BOOT_CHARGING: 421 case BOOT_UMS: 422 case BOOT_DFU: 423 i = 3; 424 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 425 break; 426 default: 427 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 428 } 429 430 out: 431 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT) 432 printf("Enter uboot reason: %s\n", reason[i]); 433 434 return; 435 } 436 437 const char *spl_kernel_partition(struct spl_image_info *spl, 438 struct spl_load_info *info) 439 { 440 struct bootloader_message *bmsg = NULL; 441 u32 boot_mode; 442 int ret, cnt; 443 u32 sector = 0; 444 445 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 446 disk_partition_t part_info; 447 448 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 449 if (ret >= 0) 450 sector = part_info.start; 451 #else 452 sector = CONFIG_SPL_MISC_SECTOR; 453 #endif 454 if (sector) { 455 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 456 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 457 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 458 cnt, bmsg); 459 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 460 free(bmsg); 461 return PART_RECOVERY; 462 } else { 463 free(bmsg); 464 } 465 } 466 467 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 468 469 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 470 } 471 472 static void spl_fdt_fixup_memory(struct spl_image_info *spl_image) 473 { 474 void *blob = spl_image->fdt_addr; 475 struct tag *t; 476 u64 start[CONFIG_NR_DRAM_BANKS]; 477 u64 size[CONFIG_NR_DRAM_BANKS]; 478 int i, count, err; 479 480 err = fdt_check_header(blob); 481 if (err < 0) { 482 printf("Invalid dtb\n"); 483 return; 484 } 485 486 /* Fixup memory node based on ddr_mem atags */ 487 t = atags_get_tag(ATAG_DDR_MEM); 488 if (t && t->u.ddr_mem.count) { 489 count = t->u.ddr_mem.count; 490 for (i = 0; i < count; i++) { 491 start[i] = t->u.ddr_mem.bank[i]; 492 size[i] = t->u.ddr_mem.bank[i + count]; 493 if (size[i] == 0) 494 continue; 495 debug("Adding bank: 0x%08llx - 0x%08llx (size: 0x%08llx)\n", 496 start[i], start[i] + size[i], size[i]); 497 } 498 err = fdt_fixup_memory_banks(blob, start, size, count); 499 if (err < 0) { 500 printf("Fixup kernel dtb memory node failed: %s\n", fdt_strerror(err)); 501 return; 502 } 503 } 504 505 return; 506 } 507 508 #if defined(CONFIG_SPL_ROCKCHIP_HWID_DTB) 509 int spl_find_hwid_dtb(const char *fdt_name) 510 { 511 hwid_init_data(); 512 513 return hwid_dtb_is_available(fdt_name); 514 } 515 #endif 516 #endif 517 518 void spl_perform_fixups(struct spl_image_info *spl_image) 519 { 520 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 521 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 522 #ifdef BUILD_SPL_TAG 523 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 524 #endif 525 #endif 526 #if defined(CONFIG_SPL_KERNEL_BOOT) 527 if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL) 528 spl_fdt_fixup_memory(spl_image); 529 #endif 530 return; 531 } 532 533 void spl_hang_reset(void) 534 { 535 printf("# Reset the board to bootrom #\n"); 536 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 537 /* reset is available after dm setup */ 538 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 539 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 540 do_reset(NULL, 0, 0, NULL); 541 } 542 #endif 543 } 544 545 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 546 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 547 { 548 int ret = 0; 549 550 *otp_index = 0; 551 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 552 struct udevice *dev; 553 u32 index, i, otp_version; 554 u32 bit_count; 555 556 dev = misc_otp_get_device(OTP_S); 557 if (!dev) 558 return -ENODEV; 559 560 otp_version = 0; 561 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 562 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 563 &index, 564 4)) { 565 printf("Can't read rollback index\n"); 566 return -EIO; 567 } 568 569 bit_count = fls(index); 570 otp_version += bit_count; 571 } 572 *otp_index = otp_version; 573 #endif 574 575 return ret; 576 } 577 578 static int fit_write_otp_rollback_index(u32 fit_index) 579 { 580 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 581 struct udevice *dev; 582 u32 index, i, otp_index; 583 584 if (!fit_index) 585 return 0; 586 587 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 588 return -EINVAL; 589 590 dev = misc_otp_get_device(OTP_S); 591 if (!dev) 592 return -ENODEV; 593 594 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 595 return -EIO; 596 597 if (otp_index < fit_index) { 598 /* Write new SW version to otp */ 599 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 600 /* 601 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 602 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 603 * actually be "0xffffffff >> 0". 604 */ 605 if (!fit_index) 606 break; 607 /* convert to base-1 representation */ 608 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 609 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 610 fit_index -= min(fit_index, 611 (u32)OTP_ALL_ONES_NUM_BITS); 612 if (index) { 613 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 614 &index, 615 4)) { 616 printf("Can't write rollback index\n"); 617 return -EIO; 618 } 619 } 620 } 621 } 622 #endif 623 624 return 0; 625 } 626 #endif 627 628 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 629 { 630 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 631 int ret; 632 633 ret = fit_write_otp_rollback_index(gd->rollback_index); 634 if (ret) { 635 panic("Failed to write fit rollback index %d, ret=%d", 636 gd->rollback_index, ret); 637 } 638 #endif 639 640 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 641 misc_decompress_cleanup(); 642 #endif 643 return 0; 644 } 645