1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <version.h> 9 #include <boot_rkimg.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <key.h> 13 #include <led.h> 14 #include <misc.h> 15 #include <ram.h> 16 #include <spl.h> 17 #include <optee_include/OpteeClientInterface.h> 18 #include <power/fuel_gauge.h> 19 #include <asm/arch/bootrom.h> 20 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 21 #include <asm/arch/rk_atags.h> 22 #endif 23 #include <asm/arch/pcie_ep_boot.h> 24 #include <asm/arch/sdram.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch-rockchip/sys_proto.h> 27 #include <asm/io.h> 28 #include <asm/arch/param.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 void board_return_to_bootrom(void) 33 { 34 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 35 } 36 37 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 38 }; 39 40 const char *board_spl_was_booted_from(void) 41 { 42 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 43 const char *bootdevice_ofpath = NULL; 44 45 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 46 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 47 48 if (bootdevice_ofpath) 49 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 50 __func__, bootdevice_brom_id, bootdevice_ofpath); 51 else 52 debug("%s: failed to resolve brom_bootdevice_id %x\n", 53 __func__, bootdevice_brom_id); 54 55 return bootdevice_ofpath; 56 } 57 58 u32 spl_boot_device(void) 59 { 60 u32 boot_device = BOOT_DEVICE_MMC1; 61 62 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 63 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 64 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 65 return BOOT_DEVICE_SPI; 66 #endif 67 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 68 return BOOT_DEVICE_BOOTROM; 69 70 return boot_device; 71 } 72 73 u32 spl_boot_mode(const u32 boot_device) 74 { 75 return MMCSD_MODE_RAW; 76 } 77 78 __weak void rockchip_stimer_init(void) 79 { 80 /* If Timer already enabled, don't re-init it */ 81 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 82 if ( reg & 0x1 ) 83 return; 84 #ifndef CONFIG_ARM64 85 asm volatile("mcr p15, 0, %0, c14, c0, 0" 86 : : "r"(COUNTER_FREQUENCY)); 87 #endif 88 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 89 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 90 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 91 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 92 } 93 94 __weak int arch_cpu_init(void) 95 { 96 return 0; 97 } 98 99 __weak int rk_board_init_f(void) 100 { 101 return 0; 102 } 103 104 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 105 void udelay(unsigned long usec) 106 { 107 __udelay(usec); 108 } 109 110 void hang(void) 111 { 112 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 113 for (;;) 114 ; 115 } 116 117 /** 118 * memset - Fill a region of memory with the given value 119 * @s: Pointer to the start of the area. 120 * @c: The byte to fill the area with 121 * @count: The size of the area. 122 * 123 * Do not use memset() to access IO space, use memset_io() instead. 124 */ 125 void *memset(void *s, int c, size_t count) 126 { 127 unsigned long *sl = (unsigned long *)s; 128 char *s8; 129 130 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 131 unsigned long cl = 0; 132 int i; 133 134 /* do it one word at a time (32 bits or 64 bits) while possible */ 135 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 136 for (i = 0; i < sizeof(*sl); i++) { 137 cl <<= 8; 138 cl |= c & 0xff; 139 } 140 while (count >= sizeof(*sl)) { 141 *sl++ = cl; 142 count -= sizeof(*sl); 143 } 144 } 145 #endif /* fill 8 bits at a time */ 146 s8 = (char *)sl; 147 while (count--) 148 *s8++ = c; 149 150 return s; 151 } 152 #endif 153 154 #ifdef CONFIG_SPL_DM_RESET 155 static void brom_download(void) 156 { 157 if (gd->console_evt == 0x02) { 158 printf("ctrl+b: Bootrom download!\n"); 159 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 160 do_reset(NULL, 0, 0, NULL); 161 } 162 } 163 #endif 164 165 static void spl_hotkey_init(void) 166 { 167 /* If disable console, skip getting uart reg */ 168 if (!gd || gd->flags & GD_FLG_DISABLE_CONSOLE) 169 return; 170 if (!gd->have_console) 171 return; 172 173 /* serial uclass only exists when enable CONFIG_SPL_FRAMEWORK */ 174 #ifdef CONFIG_SPL_FRAMEWORK 175 if (serial_tstc()) { 176 gd->console_evt = serial_getc(); 177 #else 178 if (debug_uart_tstc()) { 179 gd->console_evt = debug_uart_getc(); 180 #endif 181 if (gd->console_evt <= 0x1a) /* 'z' */ 182 printf("SPL Hotkey: ctrl+%c\n", 183 gd->console_evt + 'a' - 1); 184 } 185 186 return; 187 } 188 189 void board_init_f(ulong dummy) 190 { 191 #ifdef CONFIG_SPL_FRAMEWORK 192 int ret; 193 #if !defined(CONFIG_SUPPORT_TPL) 194 struct udevice *dev; 195 #endif 196 #endif 197 gd->flags = dummy; 198 rockchip_stimer_init(); 199 #define EARLY_UART 200 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 201 /* 202 * Debug UART can be used from here if required: 203 * 204 * debug_uart_init(); 205 * printch('a'); 206 * printhex8(0x1234); 207 * printascii("string"); 208 */ 209 if (!gd->serial.using_pre_serial && 210 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 211 debug_uart_init(); 212 printascii("U-Boot SPL board init"); 213 #endif 214 gd->sys_start_tick = get_ticks(); 215 #ifdef CONFIG_SPL_PCIE_EP_SUPPORT 216 rockchip_pcie_ep_init(); 217 #endif 218 #ifdef CONFIG_SPL_FRAMEWORK 219 ret = spl_early_init(); 220 if (ret) { 221 printf("spl_early_init() failed: %d\n", ret); 222 hang(); 223 } 224 #if !defined(CONFIG_SUPPORT_TPL) 225 debug("\nspl:init dram\n"); 226 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 227 if (ret) { 228 printf("DRAM init failed: %d\n", ret); 229 return; 230 } 231 #endif 232 preloader_console_init(); 233 #else 234 /* Some SoCs like rk3036 does not use any frame work */ 235 sdram_init(); 236 #endif 237 /* Get hotkey and store in gd */ 238 spl_hotkey_init(); 239 #ifdef CONFIG_SPL_DM_RESET 240 brom_download(); 241 #endif 242 arch_cpu_init(); 243 rk_board_init_f(); 244 #if defined(CONFIG_SPL_RAM_DEVICE) && defined(CONFIG_SPL_PCIE_EP_SUPPORT) 245 rockchip_pcie_ep_get_firmware(); 246 #endif 247 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 248 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 249 #endif 250 251 } 252 253 #ifdef CONFIG_SPL_LOAD_FIT 254 int board_fit_config_name_match(const char *name) 255 { 256 /* Just empty function now - can't decide what to choose */ 257 debug("%s: %s\n", __func__, name); 258 259 return 0; 260 } 261 #endif 262 263 int board_init_f_boot_flags(void) 264 { 265 int boot_flags = 0; 266 267 #ifdef CONFIG_FPGA_ROCKCHIP 268 arch_fpga_init(); 269 #endif 270 #ifdef CONFIG_PSTORE 271 param_parse_pstore(); 272 #endif 273 /* pre-loader serial */ 274 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 275 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 276 struct tag *t; 277 278 t = atags_get_tag(ATAG_SERIAL); 279 if (t) { 280 gd->serial.using_pre_serial = 1; 281 gd->serial.enable = t->u.serial.enable; 282 gd->serial.baudrate = t->u.serial.baudrate; 283 gd->serial.addr = t->u.serial.addr; 284 gd->serial.id = t->u.serial.id; 285 gd->baudrate = t->u.serial.baudrate; 286 if (!t->u.serial.enable) 287 boot_flags |= GD_FLG_DISABLE_CONSOLE; 288 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 289 t->u.serial.enable, (u32)t->u.serial.addr, 290 t->u.serial.baudrate, t->u.serial.id); 291 } else 292 #endif 293 { 294 gd->baudrate = CONFIG_BAUDRATE; 295 gd->serial.baudrate = CONFIG_BAUDRATE; 296 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 297 } 298 299 /* The highest priority to turn off (override) console */ 300 #if defined(CONFIG_DISABLE_CONSOLE) 301 boot_flags |= GD_FLG_DISABLE_CONSOLE; 302 #endif 303 304 return boot_flags; 305 } 306 307 #ifdef CONFIG_SPL_BOARD_INIT 308 __weak int rk_spl_board_init(void) 309 { 310 return 0; 311 } 312 313 static int setup_led(void) 314 { 315 #ifdef CONFIG_SPL_LED 316 struct udevice *dev; 317 char *led_name; 318 int ret; 319 320 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 321 if (!led_name) 322 return 0; 323 ret = led_get_by_label(led_name, &dev); 324 if (ret) { 325 debug("%s: get=%d\n", __func__, ret); 326 return ret; 327 } 328 ret = led_set_state(dev, LEDST_ON); 329 if (ret) 330 return ret; 331 #endif 332 333 return 0; 334 } 335 336 void spl_board_init(void) 337 { 338 int ret; 339 340 ret = setup_led(); 341 342 if (ret) { 343 debug("LED ret=%d\n", ret); 344 hang(); 345 } 346 347 rk_spl_board_init(); 348 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 349 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 350 #endif 351 return; 352 } 353 #endif 354 355 void spl_perform_fixups(struct spl_image_info *spl_image) 356 { 357 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 358 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 359 #ifdef BUILD_SPL_TAG 360 atags_set_shared_fwver(FW_SPL, "spl-"BUILD_SPL_TAG); 361 #endif 362 #endif 363 return; 364 } 365 366 #ifdef CONFIG_SPL_KERNEL_BOOT 367 static int spl_rockchip_dnl_key_pressed(void) 368 { 369 #if defined(CONFIG_SPL_INPUT) 370 return key_read(KEY_VOLUMEUP); 371 #else 372 return 0; 373 #endif 374 } 375 376 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 377 bool spl_is_low_power(void) 378 { 379 struct udevice *dev; 380 int ret, voltage; 381 382 ret = uclass_get_device(UCLASS_FG, 0, &dev); 383 if (ret) { 384 debug("Get charge display failed, ret=%d\n", ret); 385 return false; 386 } 387 388 voltage = fuel_gauge_get_voltage(dev); 389 if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD) 390 return false; 391 392 return true; 393 } 394 #endif 395 396 void spl_next_stage(struct spl_image_info *spl) 397 { 398 const char *reason[] = { "Recovery key", "Ctrl+c", "LowPwr", "Unknown" }; 399 uint32_t reg_boot_mode; 400 int i = 0; 401 402 if (spl_rockchip_dnl_key_pressed()) { 403 i = 0; 404 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 405 goto out; 406 } 407 408 if (gd->console_evt == 0x03) { 409 i = 1; 410 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 411 goto out; 412 } 413 414 #ifdef CONFIG_SPL_DM_FUEL_GAUGE 415 if (spl_is_low_power()) { 416 i = 2; 417 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 418 goto out; 419 } 420 #endif 421 422 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 423 switch (reg_boot_mode) { 424 case BOOT_COLD: 425 case BOOT_PANIC: 426 case BOOT_WATCHDOG: 427 case BOOT_NORMAL: 428 case BOOT_RECOVERY: 429 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 430 break; 431 default: 432 if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG) { 433 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 434 } else { 435 i = 3; 436 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 437 } 438 } 439 440 out: 441 if (spl->next_stage == SPL_NEXT_STAGE_UBOOT) 442 printf("Enter uboot reason: %s\n", reason[i]); 443 444 return; 445 } 446 #endif 447 448 #ifdef CONFIG_SPL_KERNEL_BOOT 449 const char *spl_kernel_partition(struct spl_image_info *spl, 450 struct spl_load_info *info) 451 { 452 struct bootloader_message *bmsg = NULL; 453 u32 boot_mode; 454 int ret, cnt; 455 u32 sector = 0; 456 457 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 458 disk_partition_t part_info; 459 460 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 461 if (ret >= 0) 462 sector = part_info.start; 463 #else 464 sector = CONFIG_SPL_MISC_SECTOR; 465 #endif 466 if (sector) { 467 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 468 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 469 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 470 cnt, bmsg); 471 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 472 free(bmsg); 473 return PART_RECOVERY; 474 } else { 475 free(bmsg); 476 } 477 } 478 479 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 480 481 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 482 } 483 #endif 484 485 void spl_hang_reset(void) 486 { 487 printf("# Reset the board to bootrom #\n"); 488 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 489 /* reset is available after dm setup */ 490 if (gd->flags & GD_FLG_SPL_EARLY_INIT) { 491 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 492 do_reset(NULL, 0, 0, NULL); 493 } 494 #endif 495 } 496 497 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 498 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 499 { 500 int ret = 0; 501 502 *otp_index = 0; 503 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 504 struct udevice *dev; 505 u32 index, i, otp_version; 506 u32 bit_count; 507 508 dev = misc_otp_get_device(OTP_S); 509 if (!dev) 510 return -ENODEV; 511 512 otp_version = 0; 513 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 514 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 515 &index, 516 4)) { 517 printf("Can't read rollback index\n"); 518 return -EIO; 519 } 520 521 bit_count = fls(index); 522 otp_version += bit_count; 523 } 524 *otp_index = otp_version; 525 #endif 526 527 return ret; 528 } 529 530 static int fit_write_otp_rollback_index(u32 fit_index) 531 { 532 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP) 533 struct udevice *dev; 534 u32 index, i, otp_index; 535 536 if (!fit_index) 537 return 0; 538 539 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 540 return -EINVAL; 541 542 dev = misc_otp_get_device(OTP_S); 543 if (!dev) 544 return -ENODEV; 545 546 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 547 return -EIO; 548 549 if (otp_index < fit_index) { 550 /* Write new SW version to otp */ 551 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 552 /* 553 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 554 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 555 * actually be "0xffffffff >> 0". 556 */ 557 if (!fit_index) 558 break; 559 /* convert to base-1 representation */ 560 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 561 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 562 fit_index -= min(fit_index, 563 (u32)OTP_ALL_ONES_NUM_BITS); 564 if (index) { 565 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 566 &index, 567 4)) { 568 printf("Can't write rollback index\n"); 569 return -EIO; 570 } 571 } 572 } 573 } 574 #endif 575 576 return 0; 577 } 578 #endif 579 580 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 581 { 582 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 583 int ret; 584 585 ret = fit_write_otp_rollback_index(gd->rollback_index); 586 if (ret) { 587 panic("Failed to write fit rollback index %d, ret=%d", 588 gd->rollback_index, ret); 589 } 590 #endif 591 592 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 593 misc_decompress_cleanup(); 594 #endif 595 return 0; 596 } 597