1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <boot_rkimg.h> 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <key.h> 12 #include <led.h> 13 #include <misc.h> 14 #include <ram.h> 15 #include <spl.h> 16 #include <optee_include/OpteeClientInterface.h> 17 #include <asm/arch/bootrom.h> 18 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 19 #include <asm/arch/rk_atags.h> 20 #endif 21 #include <asm/arch/sdram.h> 22 #include <asm/arch/boot_mode.h> 23 #include <asm/arch-rockchip/sys_proto.h> 24 #include <asm/io.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 void board_return_to_bootrom(void) 29 { 30 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 31 } 32 33 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 34 }; 35 36 const char *board_spl_was_booted_from(void) 37 { 38 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); 39 const char *bootdevice_ofpath = NULL; 40 41 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 42 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 43 44 if (bootdevice_ofpath) 45 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 46 __func__, bootdevice_brom_id, bootdevice_ofpath); 47 else 48 debug("%s: failed to resolve brom_bootdevice_id %x\n", 49 __func__, bootdevice_brom_id); 50 51 return bootdevice_ofpath; 52 } 53 54 u32 spl_boot_device(void) 55 { 56 u32 boot_device = BOOT_DEVICE_MMC1; 57 58 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ 59 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ 60 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) 61 return BOOT_DEVICE_SPI; 62 #endif 63 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 64 return BOOT_DEVICE_BOOTROM; 65 66 return boot_device; 67 } 68 69 u32 spl_boot_mode(const u32 boot_device) 70 { 71 return MMCSD_MODE_RAW; 72 } 73 74 __weak void rockchip_stimer_init(void) 75 { 76 /* If Timer already enabled, don't re-init it */ 77 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 78 if ( reg & 0x1 ) 79 return; 80 #ifndef CONFIG_ARM64 81 asm volatile("mcr p15, 0, %0, c14, c0, 0" 82 : : "r"(COUNTER_FREQUENCY)); 83 #endif 84 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 85 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); 86 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); 87 writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10); 88 } 89 90 __weak int arch_cpu_init(void) 91 { 92 return 0; 93 } 94 95 __weak int rk_board_init_f(void) 96 { 97 return 0; 98 } 99 100 #ifndef CONFIG_SPL_LIBGENERIC_SUPPORT 101 void udelay(unsigned long usec) 102 { 103 __udelay(usec); 104 } 105 106 void hang(void) 107 { 108 bootstage_error(BOOTSTAGE_ID_NEED_RESET); 109 for (;;) 110 ; 111 } 112 113 /** 114 * memset - Fill a region of memory with the given value 115 * @s: Pointer to the start of the area. 116 * @c: The byte to fill the area with 117 * @count: The size of the area. 118 * 119 * Do not use memset() to access IO space, use memset_io() instead. 120 */ 121 void *memset(void *s, int c, size_t count) 122 { 123 unsigned long *sl = (unsigned long *)s; 124 char *s8; 125 126 #if !CONFIG_IS_ENABLED(TINY_MEMSET) 127 unsigned long cl = 0; 128 int i; 129 130 /* do it one word at a time (32 bits or 64 bits) while possible */ 131 if (((ulong)s & (sizeof(*sl) - 1)) == 0) { 132 for (i = 0; i < sizeof(*sl); i++) { 133 cl <<= 8; 134 cl |= c & 0xff; 135 } 136 while (count >= sizeof(*sl)) { 137 *sl++ = cl; 138 count -= sizeof(*sl); 139 } 140 } 141 #endif /* fill 8 bits at a time */ 142 s8 = (char *)sl; 143 while (count--) 144 *s8++ = c; 145 146 return s; 147 } 148 #endif 149 150 void board_init_f(ulong dummy) 151 { 152 #ifdef CONFIG_SPL_FRAMEWORK 153 int ret; 154 #if !defined(CONFIG_SUPPORT_TPL) 155 struct udevice *dev; 156 #endif 157 #endif 158 159 rockchip_stimer_init(); 160 #define EARLY_UART 161 #if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART) 162 /* 163 * Debug UART can be used from here if required: 164 * 165 * debug_uart_init(); 166 * printch('a'); 167 * printhex8(0x1234); 168 * printascii("string"); 169 */ 170 if (!gd->serial.using_pre_serial && 171 !(gd->flags & GD_FLG_DISABLE_CONSOLE)) 172 debug_uart_init(); 173 printascii("U-Boot SPL board init"); 174 #endif 175 gd->sys_start_tick = get_ticks(); 176 #ifdef CONFIG_SPL_FRAMEWORK 177 ret = spl_early_init(); 178 if (ret) { 179 printf("spl_early_init() failed: %d\n", ret); 180 hang(); 181 } 182 #if !defined(CONFIG_SUPPORT_TPL) 183 debug("\nspl:init dram\n"); 184 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 185 if (ret) { 186 printf("DRAM init failed: %d\n", ret); 187 return; 188 } 189 #endif 190 preloader_console_init(); 191 #else 192 /* Some SoCs like rk3036 does not use any frame work */ 193 sdram_init(); 194 #endif 195 196 arch_cpu_init(); 197 rk_board_init_f(); 198 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) 199 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 200 #endif 201 202 } 203 204 #ifdef CONFIG_SPL_LOAD_FIT 205 int board_fit_config_name_match(const char *name) 206 { 207 /* Just empty function now - can't decide what to choose */ 208 debug("%s: %s\n", __func__, name); 209 210 return 0; 211 } 212 #endif 213 214 int board_init_f_boot_flags(void) 215 { 216 int boot_flags = 0; 217 218 /* pre-loader serial */ 219 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 220 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 221 struct tag *t; 222 223 224 t = atags_get_tag(ATAG_SERIAL); 225 if (t) { 226 gd->serial.using_pre_serial = 1; 227 gd->serial.enable = t->u.serial.enable; 228 gd->serial.baudrate = t->u.serial.baudrate; 229 gd->serial.addr = t->u.serial.addr; 230 gd->serial.id = t->u.serial.id; 231 gd->baudrate = t->u.serial.baudrate; 232 if (!t->u.serial.enable) 233 boot_flags |= GD_FLG_DISABLE_CONSOLE; 234 debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n", 235 t->u.serial.enable, (u32)t->u.serial.addr, 236 t->u.serial.baudrate, t->u.serial.id); 237 } else 238 #endif 239 { 240 gd->baudrate = CONFIG_BAUDRATE; 241 gd->serial.baudrate = CONFIG_BAUDRATE; 242 gd->serial.addr = CONFIG_DEBUG_UART_BASE; 243 } 244 245 /* The highest priority to turn off (override) console */ 246 #if defined(CONFIG_DISABLE_CONSOLE) 247 boot_flags |= GD_FLG_DISABLE_CONSOLE; 248 #endif 249 250 return boot_flags; 251 } 252 253 #ifdef CONFIG_SPL_BOARD_INIT 254 __weak int rk_spl_board_init(void) 255 { 256 return 0; 257 } 258 259 static int setup_led(void) 260 { 261 #ifdef CONFIG_SPL_LED 262 struct udevice *dev; 263 char *led_name; 264 int ret; 265 266 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 267 if (!led_name) 268 return 0; 269 ret = led_get_by_label(led_name, &dev); 270 if (ret) { 271 debug("%s: get=%d\n", __func__, ret); 272 return ret; 273 } 274 ret = led_set_state(dev, LEDST_ON); 275 if (ret) 276 return ret; 277 #endif 278 279 return 0; 280 } 281 282 void spl_board_init(void) 283 { 284 int ret; 285 286 ret = setup_led(); 287 288 if (ret) { 289 debug("LED ret=%d\n", ret); 290 hang(); 291 } 292 293 rk_spl_board_init(); 294 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 295 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 296 #endif 297 return; 298 } 299 #endif 300 301 void spl_perform_fixups(struct spl_image_info *spl_image) 302 { 303 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 304 atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device); 305 #endif 306 return; 307 } 308 309 #ifdef CONFIG_SPL_KERNEL_BOOT 310 static int spl_rockchip_dnl_key_pressed(void) 311 { 312 #if defined(CONFIG_SPL_INPUT) 313 return key_read(KEY_VOLUMEUP); 314 #else 315 return 0; 316 #endif 317 } 318 319 void spl_next_stage(struct spl_image_info *spl) 320 { 321 uint32_t reg_boot_mode; 322 323 if (spl_rockchip_dnl_key_pressed()) { 324 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 325 return; 326 } 327 328 reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 329 switch (reg_boot_mode) { 330 case BOOT_COLD: 331 case BOOT_PANIC: 332 case BOOT_WATCHDOG: 333 case BOOT_NORMAL: 334 case BOOT_RECOVERY: 335 spl->next_stage = SPL_NEXT_STAGE_KERNEL; 336 break; 337 default: 338 spl->next_stage = SPL_NEXT_STAGE_UBOOT; 339 } 340 } 341 #endif 342 343 #ifdef CONFIG_SPL_KERNEL_BOOT 344 const char *spl_kernel_partition(struct spl_image_info *spl, 345 struct spl_load_info *info) 346 { 347 struct bootloader_message *bmsg = NULL; 348 u32 boot_mode; 349 int ret, cnt; 350 u32 sector = 0; 351 352 #ifdef CONFIG_SPL_LIBDISK_SUPPORT 353 disk_partition_t part_info; 354 355 ret = part_get_info_by_name(info->dev, PART_MISC, &part_info); 356 if (ret >= 0) 357 sector = part_info.start; 358 #else 359 sector = CONFIG_SPL_MISC_SECTOR; 360 #endif 361 if (sector) { 362 cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len); 363 bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len); 364 ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET, 365 cnt, bmsg); 366 if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) { 367 free(bmsg); 368 return PART_RECOVERY; 369 } else { 370 free(bmsg); 371 } 372 } 373 374 boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG); 375 376 return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT; 377 } 378 #endif 379 380 void spl_hang_reset(void) 381 { 382 printf("# Reset the board to bootrom #\n"); 383 #if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT) 384 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 385 do_reset(NULL, 0, 0, NULL); 386 #endif 387 } 388 389 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 390 int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index) 391 { 392 int ret = 0; 393 394 *otp_index = 0; 395 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) || defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V1) 396 struct udevice *dev; 397 u32 index, i, otp_version; 398 u32 bit_count; 399 400 dev = misc_otp_get_device(OTP_S); 401 if (!dev) 402 return -ENODEV; 403 404 otp_version = 0; 405 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 406 if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 407 &index, 408 4)) { 409 printf("Can't read rollback index\n"); 410 return -EIO; 411 } 412 413 bit_count = fls(index); 414 otp_version += bit_count; 415 } 416 *otp_index = otp_version; 417 #endif 418 419 return ret; 420 } 421 422 static int fit_write_otp_rollback_index(u32 fit_index) 423 { 424 #if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V2) || defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP_V1) 425 struct udevice *dev; 426 u32 index, i, otp_index; 427 428 if (!fit_index) 429 return 0; 430 431 if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32) 432 return -EINVAL; 433 434 dev = misc_otp_get_device(OTP_S); 435 if (!dev) 436 return -ENODEV; 437 438 if (fit_read_otp_rollback_index(fit_index, &otp_index)) 439 return -EIO; 440 441 if (otp_index < fit_index) { 442 /* Write new SW version to otp */ 443 for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) { 444 /* 445 * If fit_index is equal to 0, then execute 0xffffffff >> 32. 446 * But the operand can only be 0 - 31. The "0xffffffff >> 32" is 447 * actually be "0xffffffff >> 0". 448 */ 449 if (!fit_index) 450 break; 451 /* convert to base-1 representation */ 452 index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS - 453 min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS)); 454 fit_index -= min(fit_index, 455 (u32)OTP_ALL_ONES_NUM_BITS); 456 if (index) { 457 if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4, 458 &index, 459 4)) { 460 printf("Can't write rollback index\n"); 461 return -EIO; 462 } 463 } 464 } 465 } 466 #endif 467 468 return 0; 469 } 470 #endif 471 472 int spl_board_prepare_for_jump(struct spl_image_info *spl_image) 473 { 474 #ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT 475 int ret; 476 477 ret = fit_write_otp_rollback_index(gd->rollback_index); 478 if (ret) { 479 panic("Failed to write fit rollback index %d, ret=%d", 480 gd->rollback_index, ret); 481 } 482 #endif 483 484 #ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS 485 misc_decompress_cleanup(); 486 #endif 487 return 0; 488 } 489