1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/grf_px30.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/armv8/mmu.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <dt-bindings/clock/px30-cru.h> 16 17 #define PMU_PWRDN_CON 0xff000018 18 19 static struct mm_region px30_mem_map[] = { 20 { 21 .virt = 0x0UL, 22 .phys = 0x0UL, 23 .size = 0xff000000UL, 24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 25 PTE_BLOCK_INNER_SHARE 26 }, { 27 .virt = 0xff000000UL, 28 .phys = 0xff000000UL, 29 .size = 0x01000000UL, 30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 31 PTE_BLOCK_NON_SHARE | 32 PTE_BLOCK_PXN | PTE_BLOCK_UXN 33 }, { 34 /* List terminator */ 35 0, 36 } 37 }; 38 39 struct mm_region *mem_map = px30_mem_map; 40 41 int arch_cpu_init(void) 42 { 43 #ifdef CONFIG_SPL_BUILD 44 /* We do some SoC one time setting here. */ 45 /* Disable the ddr secure region setting to make it non-secure */ 46 #endif 47 /* Enable PD_VO (default disable at reset) */ 48 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 49 50 return 0; 51 } 52 #define GRF_BASE 0xff140000 53 void board_debug_uart_init(void) 54 { 55 static struct px30_grf * const grf = (void *)GRF_BASE; 56 #ifdef CONFIG_SPL_BUILD 57 /* Do not set the iomux in U-Boot proper because SD card may using it */ 58 /* Enable early UART2 channel m0 on the px30 */ 59 rk_clrsetreg(&grf->gpio1dl_iomux, 60 GPIO1D3_MASK | GPIO1D2_MASK, 61 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 62 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 63 #endif 64 /* Set channel C as UART2 input */ 65 rk_clrsetreg(&grf->iofunc_con0, 66 CON_IOMUX_UART2SEL_MASK, 67 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 68 } 69 70 int set_armclk_rate(void) 71 { 72 struct px30_clk_priv *priv; 73 struct clk clk; 74 int ret; 75 76 ret = rockchip_get_clk(&clk.dev); 77 if (ret) { 78 printf("Failed to get clk dev\n"); 79 return ret; 80 } 81 clk.id = ARMCLK; 82 priv = dev_get_priv(clk.dev); 83 ret = clk_set_rate(&clk, priv->armclk_hz); 84 if (ret < 0) { 85 printf("Failed to set armclk %lu\n", priv->armclk_hz); 86 return ret; 87 } 88 89 return 0; 90 } 91