1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/grf_px30.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/armv8/mmu.h> 11 12 #define PMU_PWRDN_CON 0xff000018 13 14 static struct mm_region px30_mem_map[] = { 15 { 16 .virt = 0x0UL, 17 .phys = 0x0UL, 18 .size = 0xff000000UL, 19 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 20 PTE_BLOCK_INNER_SHARE 21 }, { 22 .virt = 0xff000000UL, 23 .phys = 0xff000000UL, 24 .size = 0x01000000UL, 25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 26 PTE_BLOCK_NON_SHARE | 27 PTE_BLOCK_PXN | PTE_BLOCK_UXN 28 }, { 29 /* List terminator */ 30 0, 31 } 32 }; 33 34 struct mm_region *mem_map = px30_mem_map; 35 36 int arch_cpu_init(void) 37 { 38 #ifdef CONFIG_SPL_BUILD 39 /* We do some SoC one time setting here. */ 40 /* Disable the ddr secure region setting to make it non-secure */ 41 #endif 42 /* Enable PD_VO (default disable at reset) */ 43 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 44 45 return 0; 46 } 47 #define GRF_BASE 0xff140000 48 void board_debug_uart_init(void) 49 { 50 static struct px30_grf * const grf = (void *)GRF_BASE; 51 /* Enable early UART2 channel m0 on the px30 */ 52 rk_clrsetreg(&grf->gpio1dl_iomux, 53 GPIO1D3_MASK | GPIO1D2_MASK, 54 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 55 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 56 /* Set channel C as UART2 input */ 57 rk_clrsetreg(&grf->iofunc_con0, 58 CON_IOMUX_UART2SEL_MASK, 59 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 60 } 61