1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/cru_px30.h> 11 #include <asm/arch/grf_px30.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/uart.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cru_px30.h> 16 #include <dt-bindings/clock/px30-cru.h> 17 18 #define PMU_PWRDN_CON 0xff000018 19 #define GRF_CPU_CON1 0xff140504 20 21 #define VIDEO_PHY_BASE 0xff2e0000 22 #define FW_DDR_CON_REG 0xff534040 23 #define SERVICE_CORE_ADDR 0xff508000 24 #define QOS_PRIORITY 0x08 25 26 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 27 28 #ifdef CONFIG_ARM64 29 #include <asm/armv8/mmu.h> 30 31 static struct mm_region px30_mem_map[] = { 32 { 33 .virt = 0x0UL, 34 .phys = 0x0UL, 35 .size = 0xff000000UL, 36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 37 PTE_BLOCK_INNER_SHARE 38 }, { 39 .virt = 0xff000000UL, 40 .phys = 0xff000000UL, 41 .size = 0x01000000UL, 42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 43 PTE_BLOCK_NON_SHARE | 44 PTE_BLOCK_PXN | PTE_BLOCK_UXN 45 }, { 46 /* List terminator */ 47 0, 48 } 49 }; 50 51 struct mm_region *mem_map = px30_mem_map; 52 #endif 53 54 int arch_cpu_init(void) 55 { 56 #ifdef CONFIG_SPL_BUILD 57 /* We do some SoC one time setting here. */ 58 /* Disable the ddr secure region setting to make it non-secure */ 59 writel(0x0, FW_DDR_CON_REG); 60 #endif 61 /* Enable PD_VO (default disable at reset) */ 62 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 63 64 #ifdef CONFIG_SPL_BUILD 65 /* Set cpu qos priority */ 66 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); 67 #endif 68 69 /* Disable video phy bandgap by default */ 70 writel(0x82, VIDEO_PHY_BASE + 0x0000); 71 writel(0x05, VIDEO_PHY_BASE + 0x03ac); 72 73 /* Clear the force_jtag */ 74 rk_clrreg(GRF_CPU_CON1, 1 << 7); 75 76 return 0; 77 } 78 79 #define GRF_BASE 0xff140000 80 #define UART2_BASE 0xff160000 81 #define CRU_BASE 0xff2b0000 82 void board_debug_uart_init(void) 83 { 84 static struct px30_grf * const grf = (void *)GRF_BASE; 85 86 /* GRF_IOFUNC_CON0 */ 87 enum { 88 CON_IOMUX_UART2SEL_SHIFT = 10, 89 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 90 CON_IOMUX_UART2SEL_M0 = 0, 91 CON_IOMUX_UART2SEL_M1, 92 CON_IOMUX_UART2SEL_USBPHY, 93 }; 94 95 #ifdef CONFIG_TPL_BUILD 96 static struct px30_cru * const cru = (void *)CRU_BASE; 97 static struct rk_uart * const uart = (void *)UART2_BASE; 98 99 /* GRF_GPIO2BH_IOMUX */ 100 enum { 101 GPIO2B7_SHIFT = 12, 102 GPIO2B7_MASK = 0xf << GPIO2B7_SHIFT, 103 GPIO2B7_GPIO = 0, 104 GPIO2B7_CIF_D10M0, 105 GPIO2B7_I2C2_SCL, 106 107 GPIO2B6_SHIFT = 8, 108 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, 109 GPIO2B6_GPIO = 0, 110 GPIO2B6_CIF_D1M0, 111 GPIO2B6_UART2_RXM1, 112 113 GPIO2B5_SHIFT = 4, 114 GPIO2B5_MASK = 0xf << GPIO2B5_SHIFT, 115 GPIO2B5_GPIO = 0, 116 GPIO2B5_PWM2, 117 118 GPIO2B4_SHIFT = 0, 119 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, 120 GPIO2B4_GPIO = 0, 121 GPIO2B4_CIF_D0M0, 122 GPIO2B4_UART2_TXM1, 123 }; 124 125 /* uart_sel_clk default select 24MHz */ 126 rk_clrsetreg(&cru->clksel_con[37], 127 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, 128 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); 129 rk_clrsetreg(&cru->clksel_con[38], 130 UART2_CLK_SEL_MASK, 131 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); 132 133 /* Enable early UART2 */ 134 rk_clrsetreg(&grf->iofunc_con0, 135 CON_IOMUX_UART2SEL_MASK, 136 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); 137 138 /* 139 * Set iomux to UART2_M0 and UART2_M1. 140 * Because uart2_rxm0 and uart2_txm0 are default reset value, 141 * so only need set uart2_rxm1 and uart2_txm1 here. 142 */ 143 rk_clrsetreg(&grf->gpio2bh_iomux, 144 GPIO2B6_MASK, 145 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT); 146 rk_clrsetreg(&grf->gpio2bh_iomux, 147 GPIO2B4_MASK, 148 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); 149 150 /* enable FIFO */ 151 writel(0x1, &uart->sfe); 152 #else 153 #ifdef CONFIG_SPL_BUILD 154 /* GRF_GPIO1DL_IOMUX */ 155 enum { 156 GPIO1D3_SHIFT = 12, 157 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 158 GPIO1D3_GPIO = 0, 159 GPIO1D3_SDMMC_D1, 160 GPIO1D3_UART2_RXM0, 161 162 GPIO1D2_SHIFT = 8, 163 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 164 GPIO1D2_GPIO = 0, 165 GPIO1D2_SDMMC_D0, 166 GPIO1D2_UART2_TXM0, 167 168 GPIO1D1_SHIFT = 4, 169 GPIO1D1_MASK = 0xf << GPIO1D1_SHIFT, 170 GPIO1D1_GPIO = 0, 171 GPIO1D1_SDIO_D3, 172 173 GPIO1D0_SHIFT = 0, 174 GPIO1D0_MASK = 0xf << GPIO1D0_SHIFT, 175 GPIO1D0_GPIO = 0, 176 GPIO1D0_SDIO_D2, 177 }; 178 179 /* Do not set the iomux in U-Boot proper because SD card may using it */ 180 /* Enable early UART2 channel m0 on the px30 */ 181 rk_clrsetreg(&grf->gpio1dl_iomux, 182 GPIO1D3_MASK | GPIO1D2_MASK, 183 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 184 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 185 #endif 186 /* Set channel C as UART2 input */ 187 rk_clrsetreg(&grf->iofunc_con0, 188 CON_IOMUX_UART2SEL_MASK, 189 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 190 #endif 191 } 192 193 int set_armclk_rate(void) 194 { 195 struct px30_clk_priv *priv; 196 struct clk clk; 197 int ret; 198 199 ret = rockchip_get_clk(&clk.dev); 200 if (ret) { 201 printf("Failed to get clk dev\n"); 202 return ret; 203 } 204 clk.id = ARMCLK; 205 priv = dev_get_priv(clk.dev); 206 ret = clk_set_rate(&clk, priv->armclk_hz); 207 if (ret < 0) { 208 printf("Failed to set armclk %lu\n", priv->armclk_hz); 209 return ret; 210 } 211 priv->set_armclk_rate = true; 212 213 return 0; 214 } 215