1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/cru_px30.h> 12 #include <asm/arch/grf_px30.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/uart.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/cru_px30.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 #define PMU_PWRDN_CON 0xff000018 21 #define GRF_CPU_CON1 0xff140504 22 23 #define VIDEO_PHY_BASE 0xff2e0000 24 #define FW_DDR_CON_REG 0xff534040 25 #define SERVICE_CORE_ADDR 0xff508000 26 #define QOS_PRIORITY 0x08 27 28 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 29 30 #ifdef CONFIG_ARM64 31 #include <asm/armv8/mmu.h> 32 33 static struct mm_region px30_mem_map[] = { 34 { 35 .virt = 0x0UL, 36 .phys = 0x0UL, 37 .size = 0xff000000UL, 38 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 39 PTE_BLOCK_INNER_SHARE 40 }, { 41 .virt = 0xff000000UL, 42 .phys = 0xff000000UL, 43 .size = 0x01000000UL, 44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 45 PTE_BLOCK_NON_SHARE | 46 PTE_BLOCK_PXN | PTE_BLOCK_UXN 47 }, { 48 /* List terminator */ 49 0, 50 } 51 }; 52 53 struct mm_region *mem_map = px30_mem_map; 54 #endif 55 56 #define PMU_PWRDN_CON 0xff000018 57 #define GRF_BASE 0xff140000 58 #define CRU_BASE 0xff2b0000 59 #define VIDEO_PHY_BASE 0xff2e0000 60 #define SERVICE_CORE_ADDR 0xff508000 61 #define DDR_FW_BASE 0xff534000 62 63 #define FW_DDR_CON 0x40 64 65 #define QOS_PRIORITY 0x08 66 67 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 68 69 #define GRF_GPIO1A_DS2 0x0090 70 #define GRF_GPIO1B_DS2 0x0094 71 #define GRF_GPIO1A_E 0x00F0 72 #define GRF_GPIO1B_E 0x00F4 73 74 /* GRF_GPIO1CL_IOMUX */ 75 enum { 76 GPIO1C1_SHIFT = 4, 77 GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT, 78 GPIO1C1_GPIO = 0, 79 GPIO1C1_UART1_TX, 80 81 GPIO1C0_SHIFT = 0, 82 GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT, 83 GPIO1C0_GPIO = 0, 84 GPIO1C0_UART1_RX, 85 }; 86 87 /* GRF_GPIO1DL_IOMUX */ 88 enum { 89 GPIO1D3_SHIFT = 12, 90 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 91 GPIO1D3_GPIO = 0, 92 GPIO1D3_SDMMC_D1, 93 GPIO1D3_UART2_RXM0, 94 95 GPIO1D2_SHIFT = 8, 96 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 97 GPIO1D2_GPIO = 0, 98 GPIO1D2_SDMMC_D0, 99 GPIO1D2_UART2_TXM0, 100 }; 101 102 /* GRF_GPIO1DH_IOMUX */ 103 enum { 104 GPIO1D7_SHIFT = 12, 105 GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT, 106 GPIO1D7_GPIO = 0, 107 GPIO1D7_SDMMC_CMD, 108 109 GPIO1D6_SHIFT = 8, 110 GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT, 111 GPIO1D6_GPIO = 0, 112 GPIO1D6_SDMMC_CLK, 113 114 GPIO1D5_SHIFT = 4, 115 GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT, 116 GPIO1D5_GPIO = 0, 117 GPIO1D5_SDMMC_D3, 118 119 GPIO1D4_SHIFT = 0, 120 GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT, 121 GPIO1D4_GPIO = 0, 122 GPIO1D4_SDMMC_D2, 123 }; 124 125 /* GRF_GPIO2BH_IOMUX */ 126 enum { 127 GPIO2B6_SHIFT = 8, 128 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, 129 GPIO2B6_GPIO = 0, 130 GPIO2B6_CIF_D1M0, 131 GPIO2B6_UART2_RXM1, 132 133 GPIO2B4_SHIFT = 0, 134 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, 135 GPIO2B4_GPIO = 0, 136 GPIO2B4_CIF_D0M0, 137 GPIO2B4_UART2_TXM1, 138 }; 139 140 /* GRF_GPIO3AL_IOMUX */ 141 enum { 142 GPIO3A2_SHIFT = 8, 143 GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT, 144 GPIO3A2_GPIO = 0, 145 GPIO3A2_UART5_TX = 4, 146 147 GPIO3A1_SHIFT = 4, 148 GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT, 149 GPIO3A1_GPIO = 0, 150 GPIO3A1_UART5_RX = 4, 151 }; 152 153 enum { 154 IOVSEL6_CTRL_SHIFT = 0, 155 IOVSEL6_CTRL_MASK = BIT(0), 156 VCCIO6_SEL_BY_GPIO = 0, 157 VCCIO6_SEL_BY_IOVSEL6, 158 159 IOVSEL6_SHIFT = 1, 160 IOVSEL6_MASK = BIT(1), 161 VCCIO6_3V3 = 0, 162 VCCIO6_1V8, 163 }; 164 165 /* 166 * The voltage of VCCIO6(which is the voltage domain of emmc/flash/sfc 167 * interface) can indicated by GPIO0_B6 or io_vsel6. The SOC defaults 168 * use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware, 169 * then we can switch to io_vsel6 after system power on, and release GPIO0_B6 170 * for other usage. 171 */ 172 173 #define GPIO0_B6 14 174 #define GPIO0_BASE 0xff040000 175 #define GPIO_SWPORTA_DDR 0x4 176 #define GPIO_EXT_PORTA 0x50 177 178 static int grf_vccio6_vsel_init(void) 179 { 180 static struct px30_grf * const grf = (void *)GRF_BASE; 181 u32 val; 182 183 val = readl(GPIO0_BASE + GPIO_SWPORTA_DDR); 184 val &= ~BIT(GPIO0_B6); 185 writel(val, GPIO0_BASE + GPIO_SWPORTA_DDR); 186 187 if (readl(GPIO0_BASE + GPIO_EXT_PORTA) & BIT(GPIO0_B6)) 188 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 189 VCCIO6_1V8 << IOVSEL6_SHIFT; 190 else 191 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 192 VCCIO6_3V3 << IOVSEL6_SHIFT; 193 rk_clrsetreg(&grf->io_vsel, IOVSEL6_CTRL_MASK | IOVSEL6_MASK, val); 194 195 return 0; 196 } 197 198 int arch_cpu_init(void) 199 { 200 #ifdef CONFIG_SPL_BUILD 201 /* We do some SoC one time setting here. */ 202 /* Disable the ddr secure region setting to make it non-secure */ 203 writel(0x0, FW_DDR_CON_REG); 204 205 if (soc_is_px30s()) { 206 /* set the emmc data(GPIO1A0-A7) drive strength to 14.2ma */ 207 writel(0xFFFF0000, GRF_BASE + GRF_GPIO1A_DS2); 208 writel(0xFFFFFFFF, GRF_BASE + GRF_GPIO1A_E); 209 /* set the emmc clock(GPIO1B1) drive strength to 23.7ma */ 210 /* set the emmc cmd(GPIO1B2) drive strength to 14.2ma */ 211 writel(0x00060002, GRF_BASE + GRF_GPIO1B_DS2); 212 writel(0x003C0038, GRF_BASE + GRF_GPIO1B_E); 213 } 214 #endif 215 /* Enable PD_VO (default disable at reset) */ 216 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 217 218 #ifdef CONFIG_SPL_BUILD 219 /* Set cpu qos priority */ 220 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); 221 222 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \ 223 (CONFIG_DEBUG_UART_BASE != 0xff160000) || \ 224 (CONFIG_DEBUG_UART_CHANNEL != 0) 225 static struct px30_grf * const grf = (void *)GRF_BASE; 226 /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */ 227 rk_clrsetreg(&grf->gpio1dl_iomux, 228 GPIO1D3_MASK | GPIO1D2_MASK, 229 GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT | 230 GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT); 231 rk_clrsetreg(&grf->gpio1dh_iomux, 232 GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK, 233 GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT | 234 GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT | 235 GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT | 236 GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); 237 #endif 238 239 #endif 240 241 /* Enable PD_VO (default disable at reset) */ 242 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 243 244 /* Disable video phy bandgap by default */ 245 writel(0x82, VIDEO_PHY_BASE + 0x0000); 246 writel(0x05, VIDEO_PHY_BASE + 0x03ac); 247 248 /* Clear the force_jtag */ 249 rk_clrreg(GRF_CPU_CON1, 1 << 7); 250 251 grf_vccio6_vsel_init(); 252 253 return 0; 254 } 255 256 #define GRF_BASE 0xff140000 257 #define UART2_BASE 0xff160000 258 #define CRU_BASE 0xff2b0000 259 void board_debug_uart_init(void) 260 { 261 static struct px30_grf * const grf = (void *)GRF_BASE; 262 static struct px30_cru * const cru = (void *)CRU_BASE; 263 264 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000) 265 /* uart_sel_clk default select 24MHz */ 266 rk_clrsetreg(&cru->clksel_con[34], 267 UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK, 268 UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0); 269 rk_clrsetreg(&cru->clksel_con[35], 270 UART1_CLK_SEL_MASK, 271 UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT); 272 273 rk_clrsetreg(&grf->gpio1cl_iomux, 274 GPIO1C1_MASK | GPIO1C0_MASK, 275 GPIO1C1_UART1_TX << GPIO1C1_SHIFT | 276 GPIO1C0_UART1_RX << GPIO1C0_SHIFT); 277 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000) 278 /* uart_sel_clk default select 24MHz */ 279 rk_clrsetreg(&cru->clksel_con[46], 280 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, 281 UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0); 282 rk_clrsetreg(&cru->clksel_con[47], 283 UART5_CLK_SEL_MASK, 284 UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT); 285 286 rk_clrsetreg(&grf->gpio3al_iomux, 287 GPIO3A2_MASK | GPIO3A1_MASK, 288 GPIO3A2_UART5_TX << GPIO3A2_SHIFT | 289 GPIO3A1_UART5_RX << GPIO3A1_SHIFT); 290 #else 291 /* GRF_IOFUNC_CON0 */ 292 enum { 293 CON_IOMUX_UART2SEL_SHIFT = 10, 294 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 295 CON_IOMUX_UART2SEL_M0 = 0, 296 CON_IOMUX_UART2SEL_M1, 297 CON_IOMUX_UART2SEL_USBPHY, 298 }; 299 300 /* uart_sel_clk default select 24MHz */ 301 rk_clrsetreg(&cru->clksel_con[37], 302 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, 303 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); 304 rk_clrsetreg(&cru->clksel_con[38], 305 UART2_CLK_SEL_MASK, 306 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); 307 308 #if (CONFIG_DEBUG_UART2_CHANNEL == 1) 309 /* Enable early UART2 */ 310 rk_clrsetreg(&grf->iofunc_con0, 311 CON_IOMUX_UART2SEL_MASK, 312 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); 313 314 /* 315 * Set iomux to UART2_M0 and UART2_M1. 316 * Because uart2_rxm0 and uart2_txm0 are default reset value, 317 * so only need set uart2_rxm1 and uart2_txm1 here. 318 */ 319 rk_clrsetreg(&grf->gpio2bh_iomux, 320 GPIO2B6_MASK | GPIO2B4_MASK, 321 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT | 322 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); 323 #else 324 rk_clrsetreg(&grf->iofunc_con0, 325 CON_IOMUX_UART2SEL_MASK, 326 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 327 328 rk_clrsetreg(&grf->gpio1dl_iomux, 329 GPIO1D3_MASK | GPIO1D2_MASK, 330 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 331 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 332 #endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */ 333 334 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ 335 } 336 337 int set_armclk_rate(void) 338 { 339 struct px30_clk_priv *priv; 340 struct clk clk; 341 int ret; 342 343 ret = rockchip_get_clk(&clk.dev); 344 if (ret) { 345 printf("Failed to get clk dev\n"); 346 return ret; 347 } 348 clk.id = ARMCLK; 349 priv = dev_get_priv(clk.dev); 350 ret = clk_set_rate(&clk, priv->armclk_hz); 351 if (ret < 0) { 352 printf("Failed to set armclk %lu\n", priv->armclk_hz); 353 return ret; 354 } 355 priv->set_armclk_rate = true; 356 357 return 0; 358 } 359 360 static int fdt_fixup_cpu_opp_table(const void *blob) 361 { 362 int opp_node, cpu_node, sub_node; 363 int len; 364 u32 phandle; 365 u32 *pp; 366 367 /* Replace opp table */ 368 opp_node = fdt_path_offset(blob, "/px30s-cpu0-opp-table"); 369 if (opp_node < 0) { 370 printf("Failed to get px30s-cpu0-opp-table node\n"); 371 return -EINVAL; 372 } 373 374 phandle = fdt_get_phandle(blob, opp_node); 375 if (!phandle) { 376 printf("Failed to get cpu opp table phandle\n"); 377 return -EINVAL; 378 } 379 380 cpu_node = fdt_path_offset(blob, "/cpus"); 381 if (cpu_node < 0) { 382 printf("Failed to get cpus node\n"); 383 return -EINVAL; 384 } 385 386 fdt_for_each_subnode(sub_node, blob, cpu_node) { 387 pp = (u32 *)fdt_getprop(blob, sub_node, "operating-points-v2", 388 &len); 389 if (!pp) 390 continue; 391 pp[0] = cpu_to_fdt32(phandle); 392 } 393 394 return 0; 395 } 396 397 static int fdt_fixup_dmc_opp_table(const void *blob) 398 { 399 int opp_node, dmc_node; 400 int len; 401 u32 phandle; 402 u32 *pp; 403 404 opp_node = fdt_path_offset(blob, "/px30s-dmc-opp-table"); 405 if (opp_node < 0) { 406 printf("Failed to get px30s-dmc-opp-table node\n"); 407 return -EINVAL; 408 } 409 410 phandle = fdt_get_phandle(blob, opp_node); 411 if (!phandle) { 412 printf("Failed to get dmc opp table phandle\n"); 413 return -EINVAL; 414 } 415 416 dmc_node = fdt_path_offset(blob, "/dmc"); 417 if (dmc_node < 0) { 418 printf("Failed to get dmc node\n"); 419 return -EINVAL; 420 } 421 422 pp = (u32 *)fdt_getprop(blob, dmc_node, "operating-points-v2", &len); 423 if (!pp) 424 return 0; 425 pp[0] = cpu_to_fdt32(phandle); 426 427 return 0; 428 } 429 430 static int fdt_fixup_gpu_opp_table(const void *blob) 431 { 432 int opp_node, gpu_node; 433 int len; 434 u32 phandle; 435 u32 *pp; 436 437 opp_node = fdt_path_offset(blob, "/px30s-gpu-opp-table"); 438 if (opp_node < 0) { 439 printf("Failed to get px30s-gpu-opp-table node\n"); 440 return -EINVAL; 441 } 442 443 phandle = fdt_get_phandle(blob, opp_node); 444 if (!phandle) { 445 printf("Failed to get gpu opp table phandle\n"); 446 return -EINVAL; 447 } 448 449 gpu_node = fdt_path_offset(blob, "/gpu@ff400000"); 450 if (gpu_node < 0) { 451 printf("Failed to get gpu node\n"); 452 return -EINVAL; 453 } 454 455 pp = (u32 *)fdt_getprop(blob, gpu_node, "operating-points-v2", &len); 456 if (!pp) 457 return 0; 458 pp[0] = cpu_to_fdt32(phandle); 459 460 return 0; 461 } 462 463 static void fixup_pcfg_drive_strength(const void *blob, int noffset) 464 { 465 u32 *ds, *dss; 466 u32 val; 467 468 dss = (u32 *)fdt_getprop(blob, noffset, "drive-strength-s", NULL); 469 if (!dss) 470 return; 471 472 val = dss[0]; 473 ds = (u32 *)fdt_getprop(blob, noffset, "drive-strength", NULL); 474 if (ds) { 475 ds[0] = val; 476 } else { 477 if (fdt_setprop((void *)blob, noffset, 478 "drive-strength", &val, 4) < 0) 479 printf("Failed to add drive-strength prop\n"); 480 } 481 } 482 483 static int fdt_fixup_pcfg(const void *blob) 484 { 485 int depth1_node; 486 int depth2_node; 487 int root_node; 488 489 root_node = fdt_path_offset(blob, "/"); 490 if (root_node < 0) 491 return root_node; 492 493 fdt_for_each_subnode(depth1_node, blob, root_node) { 494 debug("depth1: %s\n", fdt_get_name(blob, depth2_node, NULL)); 495 fixup_pcfg_drive_strength(blob, depth1_node); 496 fdt_for_each_subnode(depth2_node, blob, depth1_node) { 497 debug(" depth2: %s\n", 498 fdt_get_name(blob, depth2_node, NULL)); 499 fixup_pcfg_drive_strength(blob, depth2_node); 500 } 501 } 502 503 return 0; 504 } 505 506 static int fdt_fixup_bus_apll(const void *blob) 507 { 508 char path[] = "/bus-apll"; 509 510 do_fixup_by_path((void *)blob, path, "status", "disabled", sizeof("disabled"), 0); 511 512 return 0; 513 } 514 515 static int fdt_fixup_cpu_gpu_clk(const void *blob) 516 { 517 int cpu_node, gpu_node, scmi_clk_node; 518 int len; 519 u32 phandle; 520 u32 *pp; 521 522 scmi_clk_node = fdt_path_offset(blob, "/firmware/scmi/protocol@14"); 523 if (scmi_clk_node < 0) { 524 printf("Failed to get px30s scmi clk node\n"); 525 return -EINVAL; 526 } 527 528 phandle = fdt_get_phandle(blob, scmi_clk_node); 529 if (!phandle) 530 return 0; 531 532 cpu_node = fdt_path_offset(blob, "/cpus/cpu@0"); 533 if (cpu_node < 0) { 534 printf("Failed to get px30s cpu node\n"); 535 return -EINVAL; 536 } 537 /* 538 * before fixed: 539 * clocks = <&cru ARMCLK>; 540 * after fixed: 541 * clocks = <&scmi_clk 0>; 542 */ 543 pp = (u32 *)fdt_getprop(blob, cpu_node, 544 "clocks", 545 &len); 546 if (!pp) 547 return 0; 548 if ((len / 8) >= 1) { 549 pp[0] = cpu_to_fdt32(phandle); 550 pp[1] = cpu_to_fdt32(0); 551 } 552 553 gpu_node = fdt_path_offset(blob, "/gpu@ff400000"); 554 if (gpu_node < 0) { 555 printf("Failed to get px30s gpu node\n"); 556 return -EINVAL; 557 } 558 /* 559 * before fixed: 560 * clocks = <&cru SCLK_GPU>; 561 * after fixed: 562 * clocks = <&scmi_clk 1>; 563 */ 564 pp = (u32 *)fdt_getprop(blob, gpu_node, 565 "clocks", 566 &len); 567 if (!pp) 568 return 0; 569 if ((len / 8) >= 1) { 570 pp[0] = cpu_to_fdt32(phandle); 571 pp[1] = cpu_to_fdt32(1); 572 } 573 return 0; 574 } 575 576 static int fdt_fixup_i2s_soft_reset(const void *blob) 577 { 578 int node; 579 int len; 580 u32 *pp; 581 582 node = fdt_path_offset(blob, "/i2s@ff060000"); 583 if (node < 0) { 584 printf("Failed to get px30s i2s node\n"); 585 return -EINVAL; 586 } 587 588 /* 589 * before fixed: 590 * resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 591 * after fixed: 592 * resets = <&cru SRST_I2S0_TX>, <&cru 128>; 593 */ 594 pp = (u32 *)fdt_getprop(blob, node, 595 "resets", 596 &len); 597 if (!pp) 598 return 0; 599 if ((len / 8) >= 2) 600 pp[3] = cpu_to_fdt32(128); 601 602 return 0; 603 } 604 605 int rk_board_fdt_fixup(const void *blob) 606 { 607 if (soc_is_px30s()) { 608 fdt_increase_size((void *)blob, SZ_8K); 609 fdt_fixup_cpu_opp_table(blob); 610 fdt_fixup_dmc_opp_table(blob); 611 fdt_fixup_gpu_opp_table(blob); 612 fdt_fixup_pcfg(blob); 613 fdt_fixup_bus_apll(blob); 614 fdt_fixup_cpu_gpu_clk(blob); 615 fdt_fixup_i2s_soft_reset(blob); 616 } 617 618 return 0; 619 } 620 621 int rk_board_early_fdt_fixup(const void *blob) 622 { 623 rk_board_fdt_fixup(blob); 624 625 return 0; 626 } 627 628 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP) 629 int rk_board_init(void) 630 { 631 struct udevice *dev; 632 u32 ret = 0; 633 634 ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev); 635 if (ret) { 636 printf("dmc_fsp failed, ret=%d\n", ret); 637 return 0; 638 } 639 640 return 0; 641 } 642 #endif 643