1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/cru_px30.h> 12 #include <asm/arch/grf_px30.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/uart.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/cru_px30.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 #define PMU_PWRDN_CON 0xff000018 21 #define GRF_CPU_CON1 0xff140504 22 23 #define USBPHY_GRF_BASE 0xff2c0000 24 #define VIDEO_PHY_BASE 0xff2e0000 25 #define FW_DDR_CON_REG 0xff534040 26 #define SERVICE_CORE_ADDR 0xff508000 27 #define QOS_PRIORITY 0x08 28 29 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 30 31 #ifdef CONFIG_ARM64 32 #include <asm/armv8/mmu.h> 33 34 static struct mm_region px30_mem_map[] = { 35 { 36 .virt = 0x0UL, 37 .phys = 0x0UL, 38 .size = 0xff000000UL, 39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 40 PTE_BLOCK_INNER_SHARE 41 }, { 42 .virt = 0xff000000UL, 43 .phys = 0xff000000UL, 44 .size = 0x01000000UL, 45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 46 PTE_BLOCK_NON_SHARE | 47 PTE_BLOCK_PXN | PTE_BLOCK_UXN 48 }, { 49 /* List terminator */ 50 0, 51 } 52 }; 53 54 struct mm_region *mem_map = px30_mem_map; 55 #endif 56 57 #define PMU_PWRDN_CON 0xff000018 58 #define GRF_BASE 0xff140000 59 #define CRU_BASE 0xff2b0000 60 #define VIDEO_PHY_BASE 0xff2e0000 61 #define SERVICE_CORE_ADDR 0xff508000 62 #define DDR_FW_BASE 0xff534000 63 64 #define FW_DDR_CON 0x40 65 66 #define QOS_PRIORITY 0x08 67 68 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 69 70 #define GRF_GPIO1A_DS2 0x0090 71 #define GRF_GPIO1B_DS2 0x0094 72 #define GRF_GPIO1A_E 0x00F0 73 #define GRF_GPIO1B_E 0x00F4 74 75 /* GRF_GPIO1CL_IOMUX */ 76 enum { 77 GPIO1C1_SHIFT = 4, 78 GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT, 79 GPIO1C1_GPIO = 0, 80 GPIO1C1_UART1_TX, 81 82 GPIO1C0_SHIFT = 0, 83 GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT, 84 GPIO1C0_GPIO = 0, 85 GPIO1C0_UART1_RX, 86 }; 87 88 /* GRF_GPIO1DL_IOMUX */ 89 enum { 90 GPIO1D3_SHIFT = 12, 91 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 92 GPIO1D3_GPIO = 0, 93 GPIO1D3_SDMMC_D1, 94 GPIO1D3_UART2_RXM0, 95 96 GPIO1D2_SHIFT = 8, 97 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 98 GPIO1D2_GPIO = 0, 99 GPIO1D2_SDMMC_D0, 100 GPIO1D2_UART2_TXM0, 101 }; 102 103 /* GRF_GPIO1DH_IOMUX */ 104 enum { 105 GPIO1D7_SHIFT = 12, 106 GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT, 107 GPIO1D7_GPIO = 0, 108 GPIO1D7_SDMMC_CMD, 109 110 GPIO1D6_SHIFT = 8, 111 GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT, 112 GPIO1D6_GPIO = 0, 113 GPIO1D6_SDMMC_CLK, 114 115 GPIO1D5_SHIFT = 4, 116 GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT, 117 GPIO1D5_GPIO = 0, 118 GPIO1D5_SDMMC_D3, 119 120 GPIO1D4_SHIFT = 0, 121 GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT, 122 GPIO1D4_GPIO = 0, 123 GPIO1D4_SDMMC_D2, 124 }; 125 126 /* GRF_GPIO2BH_IOMUX */ 127 enum { 128 GPIO2B6_SHIFT = 8, 129 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, 130 GPIO2B6_GPIO = 0, 131 GPIO2B6_CIF_D1M0, 132 GPIO2B6_UART2_RXM1, 133 134 GPIO2B4_SHIFT = 0, 135 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, 136 GPIO2B4_GPIO = 0, 137 GPIO2B4_CIF_D0M0, 138 GPIO2B4_UART2_TXM1, 139 }; 140 141 /* GRF_GPIO3AL_IOMUX */ 142 enum { 143 GPIO3A2_SHIFT = 8, 144 GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT, 145 GPIO3A2_GPIO = 0, 146 GPIO3A2_UART5_TX = 4, 147 148 GPIO3A1_SHIFT = 4, 149 GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT, 150 GPIO3A1_GPIO = 0, 151 GPIO3A1_UART5_RX = 4, 152 }; 153 154 enum { 155 IOVSEL6_CTRL_SHIFT = 0, 156 IOVSEL6_CTRL_MASK = BIT(0), 157 VCCIO6_SEL_BY_GPIO = 0, 158 VCCIO6_SEL_BY_IOVSEL6, 159 160 IOVSEL6_SHIFT = 1, 161 IOVSEL6_MASK = BIT(1), 162 VCCIO6_3V3 = 0, 163 VCCIO6_1V8, 164 }; 165 166 /* 167 * The voltage of VCCIO6(which is the voltage domain of emmc/flash/sfc 168 * interface) can indicated by GPIO0_B6 or io_vsel6. The SOC defaults 169 * use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware, 170 * then we can switch to io_vsel6 after system power on, and release GPIO0_B6 171 * for other usage. 172 */ 173 174 #define GPIO0_B6 14 175 #define GPIO0_BASE 0xff040000 176 #define GPIO_SWPORTA_DDR 0x4 177 #define GPIO_EXT_PORTA 0x50 178 179 static int grf_vccio6_vsel_init(void) 180 { 181 static struct px30_grf * const grf = (void *)GRF_BASE; 182 u32 val; 183 184 val = readl(GPIO0_BASE + GPIO_SWPORTA_DDR); 185 val &= ~BIT(GPIO0_B6); 186 writel(val, GPIO0_BASE + GPIO_SWPORTA_DDR); 187 188 if (readl(GPIO0_BASE + GPIO_EXT_PORTA) & BIT(GPIO0_B6)) 189 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 190 VCCIO6_1V8 << IOVSEL6_SHIFT; 191 else 192 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 193 VCCIO6_3V3 << IOVSEL6_SHIFT; 194 rk_clrsetreg(&grf->io_vsel, IOVSEL6_CTRL_MASK | IOVSEL6_MASK, val); 195 196 return 0; 197 } 198 199 int arch_cpu_init(void) 200 { 201 #ifdef CONFIG_SPL_BUILD 202 /* We do some SoC one time setting here. */ 203 /* Disable the ddr secure region setting to make it non-secure */ 204 writel(0x0, FW_DDR_CON_REG); 205 206 if (soc_is_px30s()) { 207 /* set the emmc data(GPIO1A0-A7) drive strength to 14.2ma */ 208 writel(0xFFFF0000, GRF_BASE + GRF_GPIO1A_DS2); 209 writel(0xFFFFFFFF, GRF_BASE + GRF_GPIO1A_E); 210 /* set the emmc clock(GPIO1B1) drive strength to 23.7ma */ 211 /* set the emmc cmd(GPIO1B2) drive strength to 14.2ma */ 212 writel(0x00060002, GRF_BASE + GRF_GPIO1B_DS2); 213 writel(0x003C0038, GRF_BASE + GRF_GPIO1B_E); 214 } 215 #endif 216 /* Enable PD_VO (default disable at reset) */ 217 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 218 219 #ifdef CONFIG_SPL_BUILD 220 /* Set cpu qos priority */ 221 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); 222 223 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \ 224 (CONFIG_DEBUG_UART_BASE != 0xff160000) || \ 225 (CONFIG_DEBUG_UART_CHANNEL != 0) 226 static struct px30_grf * const grf = (void *)GRF_BASE; 227 /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */ 228 rk_clrsetreg(&grf->gpio1dl_iomux, 229 GPIO1D3_MASK | GPIO1D2_MASK, 230 GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT | 231 GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT); 232 rk_clrsetreg(&grf->gpio1dh_iomux, 233 GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK, 234 GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT | 235 GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT | 236 GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT | 237 GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); 238 #endif 239 240 #endif 241 242 /* Enable PD_VO (default disable at reset) */ 243 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 244 245 /* Disable video phy bandgap by default */ 246 writel(0x82, VIDEO_PHY_BASE + 0x0000); 247 writel(0x05, VIDEO_PHY_BASE + 0x03ac); 248 249 /* Clear the force_jtag */ 250 rk_clrreg(GRF_CPU_CON1, 1 << 7); 251 252 grf_vccio6_vsel_init(); 253 254 if (soc_is_px30s()) { 255 /* set usb2phy parameter */ 256 writel(0x04, USBPHY_GRF_BASE + 0x8000); 257 writel(0x46, USBPHY_GRF_BASE + 0x8004); 258 writel(0xdb, USBPHY_GRF_BASE + 0x8008); 259 writel(0x04, USBPHY_GRF_BASE + 0x8400); 260 writel(0x46, USBPHY_GRF_BASE + 0x8404); 261 writel(0xdb, USBPHY_GRF_BASE + 0x8408); 262 } 263 264 return 0; 265 } 266 267 #define GRF_BASE 0xff140000 268 #define UART2_BASE 0xff160000 269 #define CRU_BASE 0xff2b0000 270 void board_debug_uart_init(void) 271 { 272 static struct px30_grf * const grf = (void *)GRF_BASE; 273 static struct px30_cru * const cru = (void *)CRU_BASE; 274 275 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000) 276 /* uart_sel_clk default select 24MHz */ 277 rk_clrsetreg(&cru->clksel_con[34], 278 UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK, 279 UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0); 280 rk_clrsetreg(&cru->clksel_con[35], 281 UART1_CLK_SEL_MASK, 282 UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT); 283 284 rk_clrsetreg(&grf->gpio1cl_iomux, 285 GPIO1C1_MASK | GPIO1C0_MASK, 286 GPIO1C1_UART1_TX << GPIO1C1_SHIFT | 287 GPIO1C0_UART1_RX << GPIO1C0_SHIFT); 288 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000) 289 /* uart_sel_clk default select 24MHz */ 290 rk_clrsetreg(&cru->clksel_con[46], 291 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, 292 UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0); 293 rk_clrsetreg(&cru->clksel_con[47], 294 UART5_CLK_SEL_MASK, 295 UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT); 296 297 rk_clrsetreg(&grf->gpio3al_iomux, 298 GPIO3A2_MASK | GPIO3A1_MASK, 299 GPIO3A2_UART5_TX << GPIO3A2_SHIFT | 300 GPIO3A1_UART5_RX << GPIO3A1_SHIFT); 301 #else 302 /* GRF_IOFUNC_CON0 */ 303 enum { 304 CON_IOMUX_UART2SEL_SHIFT = 10, 305 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 306 CON_IOMUX_UART2SEL_M0 = 0, 307 CON_IOMUX_UART2SEL_M1, 308 CON_IOMUX_UART2SEL_USBPHY, 309 }; 310 311 /* uart_sel_clk default select 24MHz */ 312 rk_clrsetreg(&cru->clksel_con[37], 313 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, 314 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); 315 rk_clrsetreg(&cru->clksel_con[38], 316 UART2_CLK_SEL_MASK, 317 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); 318 319 #if (CONFIG_DEBUG_UART2_CHANNEL == 1) 320 /* Enable early UART2 */ 321 rk_clrsetreg(&grf->iofunc_con0, 322 CON_IOMUX_UART2SEL_MASK, 323 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); 324 325 /* 326 * Set iomux to UART2_M0 and UART2_M1. 327 * Because uart2_rxm0 and uart2_txm0 are default reset value, 328 * so only need set uart2_rxm1 and uart2_txm1 here. 329 */ 330 rk_clrsetreg(&grf->gpio2bh_iomux, 331 GPIO2B6_MASK | GPIO2B4_MASK, 332 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT | 333 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); 334 #else 335 rk_clrsetreg(&grf->iofunc_con0, 336 CON_IOMUX_UART2SEL_MASK, 337 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 338 339 rk_clrsetreg(&grf->gpio1dl_iomux, 340 GPIO1D3_MASK | GPIO1D2_MASK, 341 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 342 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 343 #endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */ 344 345 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ 346 } 347 348 int set_armclk_rate(void) 349 { 350 struct px30_clk_priv *priv; 351 struct clk clk; 352 int ret; 353 354 ret = rockchip_get_clk(&clk.dev); 355 if (ret) { 356 printf("Failed to get clk dev\n"); 357 return ret; 358 } 359 clk.id = ARMCLK; 360 priv = dev_get_priv(clk.dev); 361 ret = clk_set_rate(&clk, priv->armclk_hz); 362 if (ret < 0) { 363 printf("Failed to set armclk %lu\n", priv->armclk_hz); 364 return ret; 365 } 366 priv->set_armclk_rate = true; 367 368 return 0; 369 } 370 371 static int fdt_fixup_cpu_opp_table(const void *blob) 372 { 373 int opp_node, cpu_node, sub_node; 374 int len; 375 u32 phandle; 376 u32 *pp; 377 378 /* Replace opp table */ 379 opp_node = fdt_path_offset(blob, "/px30s-cpu0-opp-table"); 380 if (opp_node < 0) { 381 printf("Failed to get px30s-cpu0-opp-table node\n"); 382 return -EINVAL; 383 } 384 385 phandle = fdt_get_phandle(blob, opp_node); 386 if (!phandle) { 387 printf("Failed to get cpu opp table phandle\n"); 388 return -EINVAL; 389 } 390 391 cpu_node = fdt_path_offset(blob, "/cpus"); 392 if (cpu_node < 0) { 393 printf("Failed to get cpus node\n"); 394 return -EINVAL; 395 } 396 397 fdt_for_each_subnode(sub_node, blob, cpu_node) { 398 pp = (u32 *)fdt_getprop(blob, sub_node, "operating-points-v2", 399 &len); 400 if (!pp) 401 continue; 402 pp[0] = cpu_to_fdt32(phandle); 403 } 404 405 return 0; 406 } 407 408 static int fdt_fixup_dmc_opp_table(const void *blob) 409 { 410 int opp_node, dmc_node; 411 int len; 412 u32 phandle; 413 u32 *pp; 414 415 opp_node = fdt_path_offset(blob, "/px30s-dmc-opp-table"); 416 if (opp_node < 0) { 417 printf("Failed to get px30s-dmc-opp-table node\n"); 418 return -EINVAL; 419 } 420 421 phandle = fdt_get_phandle(blob, opp_node); 422 if (!phandle) { 423 printf("Failed to get dmc opp table phandle\n"); 424 return -EINVAL; 425 } 426 427 dmc_node = fdt_path_offset(blob, "/dmc"); 428 if (dmc_node < 0) { 429 printf("Failed to get dmc node\n"); 430 return -EINVAL; 431 } 432 433 pp = (u32 *)fdt_getprop(blob, dmc_node, "operating-points-v2", &len); 434 if (!pp) 435 return 0; 436 pp[0] = cpu_to_fdt32(phandle); 437 438 return 0; 439 } 440 441 static int fdt_fixup_gpu_opp_table(const void *blob) 442 { 443 int opp_node, gpu_node; 444 int len; 445 u32 phandle; 446 u32 *pp; 447 448 opp_node = fdt_path_offset(blob, "/px30s-gpu-opp-table"); 449 if (opp_node < 0) { 450 printf("Failed to get px30s-gpu-opp-table node\n"); 451 return -EINVAL; 452 } 453 454 phandle = fdt_get_phandle(blob, opp_node); 455 if (!phandle) { 456 printf("Failed to get gpu opp table phandle\n"); 457 return -EINVAL; 458 } 459 460 gpu_node = fdt_path_offset(blob, "/gpu@ff400000"); 461 if (gpu_node < 0) { 462 printf("Failed to get gpu node\n"); 463 return -EINVAL; 464 } 465 466 pp = (u32 *)fdt_getprop(blob, gpu_node, "operating-points-v2", &len); 467 if (!pp) 468 return 0; 469 pp[0] = cpu_to_fdt32(phandle); 470 471 return 0; 472 } 473 474 static void fixup_pcfg_drive_strength(const void *blob, int noffset) 475 { 476 u32 *ds, *dss; 477 u32 val; 478 479 dss = (u32 *)fdt_getprop(blob, noffset, "drive-strength-s", NULL); 480 if (!dss) 481 return; 482 483 val = dss[0]; 484 ds = (u32 *)fdt_getprop(blob, noffset, "drive-strength", NULL); 485 if (ds) { 486 ds[0] = val; 487 } else { 488 if (fdt_setprop((void *)blob, noffset, 489 "drive-strength", &val, 4) < 0) 490 printf("Failed to add drive-strength prop\n"); 491 } 492 } 493 494 static int fdt_fixup_pcfg(const void *blob) 495 { 496 int depth1_node; 497 int depth2_node; 498 int root_node; 499 500 root_node = fdt_path_offset(blob, "/"); 501 if (root_node < 0) 502 return root_node; 503 504 fdt_for_each_subnode(depth1_node, blob, root_node) { 505 debug("depth1: %s\n", fdt_get_name(blob, depth1_node, NULL)); 506 fixup_pcfg_drive_strength(blob, depth1_node); 507 fdt_for_each_subnode(depth2_node, blob, depth1_node) { 508 debug(" depth2: %s\n", 509 fdt_get_name(blob, depth2_node, NULL)); 510 fixup_pcfg_drive_strength(blob, depth2_node); 511 } 512 } 513 514 return 0; 515 } 516 517 static int fdt_fixup_bus_apll(const void *blob) 518 { 519 char path[] = "/bus-apll"; 520 521 do_fixup_by_path((void *)blob, path, "status", "disabled", sizeof("disabled"), 0); 522 523 return 0; 524 } 525 526 static int fdt_fixup_cpu_gpu_clk(const void *blob) 527 { 528 int cpu_node, gpu_node, scmi_clk_node; 529 int len; 530 u32 phandle; 531 u32 *pp; 532 533 scmi_clk_node = fdt_path_offset(blob, "/firmware/scmi/protocol@14"); 534 if (scmi_clk_node < 0) { 535 printf("Failed to get px30s scmi clk node\n"); 536 return -EINVAL; 537 } 538 539 phandle = fdt_get_phandle(blob, scmi_clk_node); 540 if (!phandle) 541 return 0; 542 543 cpu_node = fdt_path_offset(blob, "/cpus/cpu@0"); 544 if (cpu_node < 0) { 545 printf("Failed to get px30s cpu node\n"); 546 return -EINVAL; 547 } 548 /* 549 * before fixed: 550 * clocks = <&cru ARMCLK>; 551 * after fixed: 552 * clocks = <&scmi_clk 0>; 553 */ 554 pp = (u32 *)fdt_getprop(blob, cpu_node, 555 "clocks", 556 &len); 557 if (!pp) 558 return 0; 559 if ((len / 8) >= 1) { 560 pp[0] = cpu_to_fdt32(phandle); 561 pp[1] = cpu_to_fdt32(0); 562 } 563 564 gpu_node = fdt_path_offset(blob, "/gpu@ff400000"); 565 if (gpu_node < 0) { 566 printf("Failed to get px30s gpu node\n"); 567 return -EINVAL; 568 } 569 /* 570 * before fixed: 571 * clocks = <&cru SCLK_GPU>; 572 * after fixed: 573 * clocks = <&scmi_clk 1>; 574 */ 575 pp = (u32 *)fdt_getprop(blob, gpu_node, 576 "clocks", 577 &len); 578 if (!pp) 579 return 0; 580 if ((len / 8) >= 1) { 581 pp[0] = cpu_to_fdt32(phandle); 582 pp[1] = cpu_to_fdt32(1); 583 } 584 return 0; 585 } 586 587 static int fdt_fixup_i2s_soft_reset(const void *blob) 588 { 589 int node; 590 int len; 591 u32 *pp; 592 593 node = fdt_path_offset(blob, "/i2s@ff060000"); 594 if (node < 0) { 595 printf("Failed to get px30s i2s node\n"); 596 return -EINVAL; 597 } 598 599 /* 600 * before fixed: 601 * resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 602 * after fixed: 603 * resets = <&cru SRST_I2S0_TX>, <&cru 128>; 604 */ 605 pp = (u32 *)fdt_getprop(blob, node, 606 "resets", 607 &len); 608 if (!pp) 609 return 0; 610 if ((len / 8) >= 2) 611 pp[3] = cpu_to_fdt32(128); 612 613 return 0; 614 } 615 616 #define RKPM_SLP_ARMPD BIT(0) 617 #define RKPM_SLP_ARMOFF BIT(1) 618 #define RKPM_SLP_ARMOFF_DDRPD BIT(2) 619 #define RKPM_SLP_ARMOFF_LOGOFF BIT(3) 620 621 static int fdt_fixup_rockchip_suspend(const void *blob) 622 { 623 int suspend_node; 624 u32 *data, mode; 625 626 /* Replace opp table */ 627 suspend_node = fdt_path_offset(blob, "/rockchip-suspend"); 628 if (suspend_node < 0) { 629 printf("Failed to get rockchip-suspend node\n"); 630 return -EINVAL; 631 } 632 633 data = (u32 *)fdt_getprop(blob, suspend_node, 634 "rockchip,sleep-mode-config", NULL); 635 if (!data) 636 return 0; 637 638 mode = fdt32_to_cpu(*data); 639 mode &= ~RKPM_SLP_ARMOFF_LOGOFF; 640 mode |= RKPM_SLP_ARMOFF; 641 *data = cpu_to_fdt32(mode); 642 643 if (fdt_setprop((void *)blob, suspend_node, 644 "rockchip,sleep-mode-config", data, sizeof(*data))) 645 printf("Failed to set rockchip,sleep-mode-config = 0x%x\n", mode); 646 else 647 debug("set rockchip,sleep-mode-config = 0x%x\n", mode); 648 649 return 0; 650 } 651 652 static void fixup_regulators_px30s(const void *blob, int reg_node) 653 { 654 const char *name; 655 int mem_node; 656 int suspend; 657 u32 *min, *max; 658 659 min = (u32 *)fdt_getprop(blob, reg_node, 660 "regulator-min-microvolt", NULL); 661 max = (u32 *)fdt_getprop(blob, reg_node, 662 "regulator-max-microvolt", NULL); 663 if (!min || !max) 664 return; 665 666 name = fdt_getprop(blob, reg_node, "regulator-name", NULL); 667 668 debug("%s: name: %s, min %duV, max %duV\n", 669 name, fdt_get_name(blob, reg_node, NULL), 670 fdt32_to_cpu(min[0]), fdt32_to_cpu(max[0])); 671 672 /* 1. fixed volt: 1.0v => 0.9v */ 673 if (*min == *max && fdt32_to_cpu(min[0]) == 1000000) { 674 mem_node = fdt_subnode_offset(blob, reg_node, 675 "regulator-state-mem"); 676 if (mem_node < 0) 677 return; 678 679 suspend = cpu_to_fdt32(900000); 680 if (fdt_setprop((void *)blob, mem_node, 681 "regulator-suspend-microvolt", 682 &suspend, sizeof(suspend))) 683 printf("Failed to set %s suspend 0.9V\n", name); 684 else 685 debug("%s: set suspend volt 0.9V\n", name); 686 687 min[0] = cpu_to_fdt32(900000); 688 max[0] = cpu_to_fdt32(900000); 689 debug("%s: min/max 1.0v => 0.9v\n", 690 fdt_get_name(blob, reg_node, NULL)); 691 } 692 693 /* 2. vdd_logic suspend: any => 0.85v */ 694 if (!strcmp(name, "vdd_logic")) { 695 mem_node = fdt_subnode_offset(blob, reg_node, 696 "regulator-state-mem"); 697 if (mem_node < 0) 698 return; 699 700 suspend = cpu_to_fdt32(850000); 701 if (fdt_setprop((void *)blob, mem_node, 702 "regulator-suspend-microvolt", 703 &suspend, sizeof(suspend))) 704 printf("Failed to set vdd_logic suspend 0.85V\n"); 705 else 706 debug("vdd_logic: set suspend volt 0.85V\n"); 707 } 708 } 709 710 static void fixup_regulators_px30(const void *blob, int reg_node) 711 { 712 const char *name; 713 int mem_node; 714 715 name = fdt_getprop(blob, reg_node, "regulator-name", NULL); 716 if (!name) 717 return; 718 719 /* regulator-off-in-suspend => regulator-on-in-suspend */ 720 if (!strcmp(name, "vdd_logic") || 721 !strcmp(name, "vcc_3v0") || 722 !strcmp(name, "vcc_1v0") || 723 !strcmp(name, "vccio_sd") || 724 !strcmp(name, "vcc_sd")) { 725 mem_node = fdt_subnode_offset(blob, reg_node, 726 "regulator-state-mem"); 727 if (mem_node < 0) 728 return; 729 730 fdt_delprop((void *)blob, mem_node, "regulator-off-in-suspend"); 731 if (fdt_setprop((void *)blob, mem_node, 732 "regulator-on-in-suspend", NULL, 0)) 733 printf("Failed to set regulator(%s) on in suspend\n", name); 734 else 735 debug("set regulator(%s) on in suspend\n", name); 736 } 737 } 738 739 static void fixup_regulators(const void *blob, int pmic_node) 740 { 741 int parent_node; 742 int reg_node; 743 744 parent_node = fdt_subnode_offset(blob, pmic_node, "regulators"); 745 if (parent_node < 0) 746 return; 747 748 fdt_for_each_subnode(reg_node, blob, parent_node) { 749 if (soc_is_px30s()) 750 fixup_regulators_px30s(blob, reg_node); 751 else if (soc_is_px30()) 752 fixup_regulators_px30(blob, reg_node); 753 } 754 } 755 756 /* Assume that: all regulators are from rk809/817 */ 757 static int fdt_fixup_regulator(const void *blob) 758 { 759 const char *name; 760 int i2c_node; 761 int pmic_node; 762 int root_node; 763 764 root_node = fdt_path_offset(blob, "/"); 765 if (root_node < 0) 766 return root_node; 767 768 fdt_for_each_subnode(i2c_node, blob, root_node) { 769 name = fdt_get_name(blob, i2c_node, NULL); 770 debug("depth1: %s\n", name); 771 if (!strncmp(name, "i2c@", 4)) { 772 fdt_for_each_subnode(pmic_node, blob, i2c_node) { 773 name = fdt_get_name(blob, pmic_node, NULL); 774 debug("depth2: %s\n", name); 775 if (!strncmp(name, "pmic@20", 7)) { 776 fixup_regulators(blob, pmic_node); 777 return 0; 778 } 779 } 780 } 781 } 782 783 return 0; 784 } 785 786 int rk_board_fdt_fixup(const void *blob) 787 { 788 if (soc_is_px30s()) { 789 fdt_increase_size((void *)blob, SZ_8K); 790 fdt_fixup_cpu_opp_table(blob); 791 fdt_fixup_dmc_opp_table(blob); 792 fdt_fixup_gpu_opp_table(blob); 793 fdt_fixup_pcfg(blob); 794 fdt_fixup_bus_apll(blob); 795 fdt_fixup_cpu_gpu_clk(blob); 796 fdt_fixup_i2s_soft_reset(blob); 797 } else if (soc_is_px30()) { 798 fdt_fixup_rockchip_suspend(blob); 799 } 800 801 fdt_fixup_regulator(blob); 802 803 return 0; 804 } 805 806 int rk_board_early_fdt_fixup(const void *blob) 807 { 808 rk_board_fdt_fixup(blob); 809 810 return 0; 811 } 812 813 void do_board_download(void) 814 { 815 /* 816 * Maskrom download can prevent to flash px30s board with px30 817 * update.img, because px30 ddr.bin can't work on px30s which is 818 * early than download action. 819 * 820 * Let's handle that early than outside generic download. 821 */ 822 if (soc_is_px30s()) { 823 printf("Rockusb is disabled, entering bootrom...\n"); 824 flushc(); 825 run_command("rbrom", 0); 826 } 827 } 828 829 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP) 830 int rk_board_init(void) 831 { 832 struct udevice *dev; 833 u32 ret = 0; 834 835 ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev); 836 if (ret) { 837 printf("dmc_fsp failed, ret=%d\n", ret); 838 return 0; 839 } 840 841 return 0; 842 } 843 #endif 844