1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <amp.h> 8 #include <clk.h> 9 #include <bidram.h> 10 #include <dm.h> 11 #include <debug_uart.h> 12 #include <key.h> 13 #include <memblk.h> 14 #include <ram.h> 15 #include <syscon.h> 16 #include <sysmem.h> 17 #include <asm/io.h> 18 #include <asm/arch/vendor.h> 19 #include <misc.h> 20 #include <asm/gpio.h> 21 #include <dm/uclass-internal.h> 22 #include <asm/arch/clock.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/periph.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch/hotkey.h> 27 #include <asm/arch/rk_atags.h> 28 #include <asm/arch/param.h> 29 #ifdef CONFIG_DM_CHARGE_DISPLAY 30 #include <power/charge_display.h> 31 #endif 32 #ifdef CONFIG_DM_DVFS 33 #include <dvfs.h> 34 #endif 35 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 36 #include <io-domain.h> 37 #endif 38 #ifdef CONFIG_DM_REGULATOR 39 #include <power/regulator.h> 40 #endif 41 #ifdef CONFIG_DRM_ROCKCHIP 42 #include <video_rockchip.h> 43 #endif 44 #ifdef CONFIG_ROCKCHIP_DEBUGGER 45 #include <rockchip_debugger.h> 46 #endif 47 #include <of_live.h> 48 #include <dm/root.h> 49 #include <console.h> 50 51 DECLARE_GLOBAL_DATA_PTR; 52 /* define serialno max length, the max length is 512 Bytes 53 * The remaining bytes are used to ensure that the first 512 bytes 54 * are valid when executing 'env_set("serial#", value)'. 55 */ 56 #define VENDOR_SN_MAX 513 57 #define CPUID_LEN 0x10 58 #define CPUID_OFF 0x7 59 60 static int rockchip_set_ethaddr(void) 61 { 62 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 63 int ret; 64 u8 ethaddr[ARP_HLEN]; 65 char buf[ARP_HLEN_ASCII + 1]; 66 67 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 68 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 69 sprintf(buf, "%pM", ethaddr); 70 env_set("ethaddr", buf); 71 } 72 #endif 73 return 0; 74 } 75 76 static int rockchip_set_serialno(void) 77 { 78 char serialno_str[VENDOR_SN_MAX]; 79 int ret = 0, i; 80 u8 cpuid[CPUID_LEN] = {0}; 81 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 82 u64 serialno; 83 84 /* Read serial number from vendor storage part */ 85 memset(serialno_str, 0, VENDOR_SN_MAX); 86 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 87 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 88 if (ret > 0) { 89 env_set("serial#", serialno_str); 90 } else { 91 #endif 92 #ifdef CONFIG_ROCKCHIP_EFUSE 93 struct udevice *dev; 94 95 /* retrieve the device */ 96 ret = uclass_get_device_by_driver(UCLASS_MISC, 97 DM_GET_DRIVER(rockchip_efuse), &dev); 98 if (ret) { 99 printf("%s: could not find efuse device\n", __func__); 100 return ret; 101 } 102 /* read the cpu_id range from the efuses */ 103 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 104 if (ret) { 105 printf("%s: reading cpuid from the efuses failed\n", __func__); 106 return ret; 107 } 108 #else 109 /* generate random cpuid */ 110 for (i = 0; i < CPUID_LEN; i++) { 111 cpuid[i] = (u8)(rand()); 112 } 113 #endif 114 /* Generate the serial number based on CPU ID */ 115 for (i = 0; i < 8; i++) { 116 low[i] = cpuid[1 + (i << 1)]; 117 high[i] = cpuid[i << 1]; 118 } 119 serialno = crc32_no_comp(0, low, 8); 120 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 121 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 122 123 env_set("serial#", serialno_str); 124 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 125 } 126 #endif 127 return ret; 128 } 129 130 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 131 int fb_set_reboot_flag(void) 132 { 133 printf("Setting reboot to fastboot flag ...\n"); 134 /* Set boot mode to fastboot */ 135 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 136 137 return 0; 138 } 139 #endif 140 141 __weak int rk_board_init(void) 142 { 143 return 0; 144 } 145 146 __weak int rk_board_late_init(void) 147 { 148 return 0; 149 } 150 151 __weak int rk_board_fdt_fixup(void *blob) 152 { 153 return 0; 154 } 155 156 __weak int soc_clk_dump(void) 157 { 158 return 0; 159 } 160 161 __weak int set_armclk_rate(void) 162 { 163 return 0; 164 } 165 166 int board_late_init(void) 167 { 168 rockchip_set_ethaddr(); 169 rockchip_set_serialno(); 170 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 171 setup_boot_mode(); 172 #endif 173 174 #ifdef CONFIG_DM_CHARGE_DISPLAY 175 charge_display(); 176 #endif 177 178 #ifdef CONFIG_DRM_ROCKCHIP 179 rockchip_show_logo(); 180 #endif 181 182 soc_clk_dump(); 183 184 return rk_board_late_init(); 185 } 186 187 #ifdef CONFIG_USING_KERNEL_DTB 188 #include <asm/arch/resource_img.h> 189 190 /* Here, only fixup cru phandle, pmucru is not included */ 191 static int phandles_fixup(void *fdt) 192 { 193 const char *props[] = { "clocks", "assigned-clocks" }; 194 struct udevice *dev; 195 struct uclass *uc; 196 const char *comp; 197 u32 id, nclocks; 198 u32 *clocks; 199 int phandle, ncells; 200 int off, offset; 201 int ret, length; 202 int i, j; 203 int first_phandle = -1; 204 205 phandle = -ENODATA; 206 ncells = -ENODATA; 207 208 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 209 for (offset = fdt_next_node(fdt, 0, NULL); 210 offset >= 0; 211 offset = fdt_next_node(fdt, offset, NULL)) { 212 comp = fdt_getprop(fdt, offset, "compatible", NULL); 213 if (!comp) 214 continue; 215 216 /* Actually, this is not a good method to get cru node */ 217 off = strlen(comp) - strlen("-cru"); 218 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 219 phandle = fdt_get_phandle(fdt, offset); 220 ncells = fdtdec_get_int(fdt, offset, 221 "#clock-cells", -ENODATA); 222 break; 223 } 224 } 225 226 if (phandle == -ENODATA || ncells == -ENODATA) 227 return 0; 228 229 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 230 __func__, ncells, fdt32_to_cpu(phandle)); 231 232 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 233 for (id = 0; id < UCLASS_COUNT; id++) { 234 ret = uclass_get(id, &uc); 235 if (ret) 236 continue; 237 238 if (list_empty(&uc->dev_head)) 239 continue; 240 241 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 242 /* Only U-Boot node go further */ 243 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc")) 244 continue; 245 246 for (i = 0; i < ARRAY_SIZE(props); i++) { 247 if (!dev_read_prop(dev, props[i], &length)) 248 continue; 249 250 clocks = malloc(length); 251 if (!clocks) 252 return -ENOMEM; 253 254 /* Read "props[]" which contains cru phandle */ 255 nclocks = length / sizeof(u32); 256 if (dev_read_u32_array(dev, props[i], 257 clocks, nclocks)) { 258 free(clocks); 259 continue; 260 } 261 262 /* Fixup with kernel cru phandle */ 263 for (j = 0; j < nclocks; j += (ncells + 1)) { 264 /* 265 * Check: update pmucru phandle with cru 266 * phandle by mistake. 267 */ 268 if (first_phandle == -1) 269 first_phandle = clocks[j]; 270 271 if (clocks[j] != first_phandle) { 272 debug("WARN: %s: first cru phandle=%d, this=%d\n", 273 dev_read_name(dev), 274 first_phandle, clocks[j]); 275 continue; 276 } 277 278 clocks[j] = phandle; 279 } 280 281 /* 282 * Override live dt nodes but not fdt nodes, 283 * because all U-Boot nodes has been imported 284 * to live dt nodes, should use "dev_xxx()". 285 */ 286 dev_write_u32_array(dev, props[i], 287 clocks, nclocks); 288 free(clocks); 289 } 290 } 291 } 292 293 return 0; 294 } 295 296 int init_kernel_dtb(void) 297 { 298 int ret = 0; 299 ulong fdt_addr = 0; 300 301 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 302 if (!fdt_addr) { 303 printf("No Found FDT Load Address.\n"); 304 return -1; 305 } 306 307 ret = rockchip_read_dtb_file((void *)fdt_addr); 308 if (ret < 0) { 309 printf("%s dtb in resource read fail\n", __func__); 310 return 0; 311 } 312 313 /* 314 * There is a phandle miss match between U-Boot and kernel dtb node, 315 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 316 */ 317 phandles_fixup((void *)fdt_addr); 318 319 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 320 321 dm_scan_fdt((void *)fdt_addr, false); 322 323 gd->fdt_blob = (void *)fdt_addr; 324 325 /* Reserve 'reserved-memory' */ 326 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 327 if (ret) 328 return ret; 329 330 return 0; 331 } 332 #endif 333 334 void board_env_fixup(void) 335 { 336 struct memblock mem; 337 ulong u_addr_r; 338 phys_size_t end; 339 char *addr_r; 340 341 #ifdef ENV_MEM_LAYOUT_SETTINGS1 342 const char *env_addr0[] = { 343 "scriptaddr", "pxefile_addr_r", 344 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 345 }; 346 const char *env_addr1[] = { 347 "scriptaddr1", "pxefile_addr1_r", 348 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 349 }; 350 int i; 351 352 /* 128M is a typical ram size for most platform, so as default here */ 353 if (gd->ram_size <= SZ_128M) { 354 /* Replace orignal xxx_addr_r */ 355 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 356 addr_r = env_get(env_addr1[i]); 357 if (addr_r) 358 env_set(env_addr0[i], addr_r); 359 } 360 } 361 #endif 362 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 363 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 364 addr_r = env_get("kernel_addr_no_bl32_r"); 365 if (addr_r) 366 env_set("kernel_addr_r", addr_r); 367 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 368 } else { 369 mem = param_parse_optee_mem(); 370 end = mem.base + mem.size; 371 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 372 if (u_addr_r >= mem.base && u_addr_r < end) 373 env_set_hex("ramdisk_addr_r", end); 374 } 375 } 376 377 static void early_download_init(void) 378 { 379 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 380 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 381 if (pwrkey_download_init()) 382 printf("Pwrkey download init failed\n"); 383 #endif 384 385 if (!tstc()) 386 return; 387 388 gd->console_evt = getc(); 389 if (gd->console_evt <= 0x1a) /* 'z' */ 390 printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1)); 391 392 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 393 /* ctrl+b */ 394 if (is_hotkey(HK_BROM_DNL)) { 395 printf("Enter bootrom download..."); 396 flushc(); 397 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 398 do_reset(NULL, 0, 0, NULL); 399 printf("failed!\n"); 400 } 401 #endif 402 } 403 404 int board_init(void) 405 { 406 int ret; 407 408 board_debug_uart_init(); 409 410 #ifdef CONFIG_USING_KERNEL_DTB 411 init_kernel_dtb(); 412 #endif 413 early_download_init(); 414 415 /* 416 * pmucru isn't referenced on some platforms, so pmucru driver can't 417 * probe that the "assigned-clocks" is unused. 418 */ 419 clks_probe(); 420 #ifdef CONFIG_DM_REGULATOR 421 ret = regulators_enable_boot_on(false); 422 if (ret) 423 debug("%s: Cannot enable boot on regulator\n", __func__); 424 #endif 425 426 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 427 io_domain_init(); 428 #endif 429 430 set_armclk_rate(); 431 432 #ifdef CONFIG_DM_DVFS 433 dvfs_init(true); 434 #endif 435 436 return rk_board_init(); 437 } 438 439 int interrupt_debugger_init(void) 440 { 441 int ret = 0; 442 443 #ifdef CONFIG_ROCKCHIP_DEBUGGER 444 ret = rockchip_debugger_init(); 445 #endif 446 return ret; 447 } 448 449 int board_fdt_fixup(void *blob) 450 { 451 /* 452 * Common fixup for DRM 453 */ 454 #ifdef CONFIG_DRM_ROCKCHIP 455 rockchip_display_fixup(blob); 456 #endif 457 458 return rk_board_fdt_fixup(blob); 459 } 460 461 #ifdef CONFIG_ARM64_BOOT_AARCH32 462 /* 463 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 464 * 465 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 466 * 467 * Command for OP-TEE: 468 * 64-bit mode: dcache is always enabled; 469 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 470 * 471 * Command for U-Boot: 472 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 473 * regions are mapped. That's good to match OP-TEE MMU policy. 474 * 475 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 476 * the OP-TEE region has been reserved, so it can not be 477 * mapped(i.e. dcache is disabled). That's also good to match 478 * OP-TEE MMU policy. 479 * 480 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 481 * should follow OP-TEE MMU policy. 482 * 483 * Here is the special: 484 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 485 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 486 * region(but OP-TEE requires it cacheable) so we fixup here. 487 */ 488 int board_initr_caches_fixup(void) 489 { 490 struct memblock mem; 491 492 mem = param_parse_optee_mem(); 493 if (mem.size) 494 mmu_set_region_dcache_behaviour(mem.base, mem.size, 495 DCACHE_WRITEBACK); 496 return 0; 497 } 498 #endif 499 500 void board_quiesce_devices(void) 501 { 502 hotkey_run(HK_CMDLINE); 503 hotkey_run(HK_CLI); 504 505 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 506 /* Destroy atags makes next warm boot safer */ 507 atags_destroy(); 508 #endif 509 510 #if defined(CONFIG_CONSOLE_RECORD) 511 /* Print record console data */ 512 console_record_print_purge(); 513 #endif 514 } 515 516 void enable_caches(void) 517 { 518 icache_enable(); 519 dcache_enable(); 520 } 521 522 #ifdef CONFIG_LMB 523 /* 524 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 525 * This makes lmb_alloc_base() always alloc from tail of sdram. 526 * If we don't assign it, bi_dram[0] is used by default and it may cause 527 * lmb_alloc_base() fail when bi_dram[0] range is small. 528 */ 529 void board_lmb_reserve(struct lmb *lmb) 530 { 531 u64 start, size; 532 char bootm_low[32]; 533 char bootm_mapsize[32]; 534 int i; 535 536 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 537 if (!gd->bd->bi_dram[i].size) 538 break; 539 } 540 541 start = gd->bd->bi_dram[i - 1].start; 542 size = gd->bd->bi_dram[i - 1].size; 543 544 /* 545 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 546 * otherwise "Unable to handle kernel paging request at virtual address ...". 547 * 548 * So that we hope limit highest address at 768M, but there comes the the 549 * problem: ramdisk is a compressed image and it expands after descompress, 550 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 551 * 552 * We make a appointment that the highest memory address is 512MB, it 553 * makes lmb alloc safer. 554 */ 555 #ifndef CONFIG_ARM64 556 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 557 start = gd->bd->bi_dram[i - 2].start; 558 size = gd->bd->bi_dram[i - 2].size; 559 } 560 561 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 562 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 563 #endif 564 sprintf(bootm_low, "0x%llx", start); 565 sprintf(bootm_mapsize, "0x%llx", size); 566 env_set("bootm_low", bootm_low); 567 env_set("bootm_mapsize", bootm_mapsize); 568 } 569 #endif 570 571 #ifdef CONFIG_BIDRAM 572 int board_bidram_reserve(struct bidram *bidram) 573 { 574 struct memblock mem; 575 int ret; 576 577 /* ATF */ 578 mem = param_parse_atf_mem(); 579 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 580 if (ret) 581 return ret; 582 583 /* PSTORE/ATAGS/SHM */ 584 mem = param_parse_common_resv_mem(); 585 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 586 if (ret) 587 return ret; 588 589 /* OP-TEE */ 590 mem = param_parse_optee_mem(); 591 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 592 if (ret) 593 return ret; 594 595 return 0; 596 } 597 598 parse_fn_t board_bidram_parse_fn(void) 599 { 600 return param_parse_ddr_mem; 601 } 602 #endif 603 604 #ifdef CONFIG_ROCKCHIP_AMP 605 void cpu_secondary_init_r(void) 606 { 607 amp_cpus_on(); 608 } 609 #endif 610 611 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 612 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 613 int board_init_f_init_serial(void) 614 { 615 struct tag *t = atags_get_tag(ATAG_SERIAL); 616 617 if (t) { 618 gd->serial.using_pre_serial = t->u.serial.enable; 619 gd->serial.addr = t->u.serial.addr; 620 gd->serial.baudrate = t->u.serial.baudrate; 621 gd->serial.id = t->u.serial.id; 622 623 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 624 __func__, gd->serial.using_pre_serial, 625 gd->serial.addr, gd->serial.baudrate, 626 gd->serial.id); 627 } 628 629 return 0; 630 } 631 #endif 632 633 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 634 #include <fdt_support.h> 635 #include <usb.h> 636 #include <usb/dwc2_udc.h> 637 638 static struct dwc2_plat_otg_data otg_data = { 639 .rx_fifo_sz = 512, 640 .np_tx_fifo_sz = 16, 641 .tx_fifo_sz = 128, 642 }; 643 644 int board_usb_init(int index, enum usb_init_type init) 645 { 646 int node; 647 fdt_addr_t addr; 648 const fdt32_t *reg; 649 const void *blob = gd->fdt_blob; 650 651 /* find the usb_otg node */ 652 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 653 654 retry: 655 if (node > 0) { 656 reg = fdt_getprop(blob, node, "reg", NULL); 657 if (!reg) 658 return -EINVAL; 659 660 addr = fdt_translate_address(blob, node, reg); 661 if (addr == OF_BAD_ADDR) { 662 pr_err("Not found usb_otg address\n"); 663 return -EINVAL; 664 } 665 666 #if defined(CONFIG_ROCKCHIP_RK3288) 667 if (addr != 0xff580000) { 668 node = fdt_node_offset_by_compatible(blob, node, 669 "snps,dwc2"); 670 goto retry; 671 } 672 #endif 673 } else { 674 /* 675 * With kernel dtb support, rk3288 dwc2 otg node 676 * use the rockchip legacy dwc2 driver "dwc_otg_310" 677 * with the compatible "rockchip,rk3288_usb20_otg", 678 * and rk3368 also use the "dwc_otg_310" driver with 679 * the compatible "rockchip,rk3368-usb". 680 */ 681 #if defined(CONFIG_ROCKCHIP_RK3288) 682 node = fdt_node_offset_by_compatible(blob, -1, 683 "rockchip,rk3288_usb20_otg"); 684 #elif defined(CONFIG_ROCKCHIP_RK3368) 685 node = fdt_node_offset_by_compatible(blob, -1, 686 "rockchip,rk3368-usb"); 687 #endif 688 if (node > 0) { 689 goto retry; 690 } else { 691 pr_err("Not found usb_otg device\n"); 692 return -ENODEV; 693 } 694 } 695 696 otg_data.regs_otg = (uintptr_t)addr; 697 698 return dwc2_udc_probe(&otg_data); 699 } 700 701 int board_usb_cleanup(int index, enum usb_init_type init) 702 { 703 return 0; 704 } 705 #endif 706