1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/system.h> 26 27 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) 28 29 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 30 #define CACHE_SETUP 0x1a 31 #else 32 #define CACHE_SETUP 0x1e 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static void cp_delay (void) 38 { 39 volatile int i; 40 41 /* copro seems to need some delay between reading and writing */ 42 for (i = 0; i < 100; i++) 43 nop(); 44 asm volatile("" : : : "memory"); 45 } 46 47 /* to activate the MMU we need to set up virtual memory: use 1M areas in bss */ 48 static inline void mmu_setup(void) 49 { 50 static u32 __attribute__((aligned(16384))) page_table[4096]; 51 bd_t *bd = gd->bd; 52 int i, j; 53 u32 reg; 54 55 /* Set up an identity-mapping for all 4GB, rw for everyone */ 56 for (i = 0; i < 4096; i++) 57 page_table[i] = i << 20 | (3 << 10) | 0x12; 58 /* Then, enable cacheable and bufferable for RAM only */ 59 for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) { 60 for (i = bd->bi_dram[j].start >> 20; 61 i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20; 62 i++) { 63 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; 64 } 65 } 66 67 /* Copy the page table address to cp15 */ 68 asm volatile("mcr p15, 0, %0, c2, c0, 0" 69 : : "r" (page_table) : "memory"); 70 /* Set the access control to all-supervisor */ 71 asm volatile("mcr p15, 0, %0, c3, c0, 0" 72 : : "r" (~0)); 73 /* and enable the mmu */ 74 reg = get_cr(); /* get control reg. */ 75 cp_delay(); 76 set_cr(reg | CR_M); 77 78 } 79 80 /* cache_bit must be either CR_I or CR_C */ 81 static void cache_enable(uint32_t cache_bit) 82 { 83 uint32_t reg; 84 85 /* The data cache is not active unless the mmu is enabled too */ 86 if (cache_bit == CR_C) 87 mmu_setup(); 88 reg = get_cr(); /* get control reg. */ 89 cp_delay(); 90 set_cr(reg | cache_bit); 91 } 92 93 /* cache_bit must be either CR_I or CR_C */ 94 static void cache_disable(uint32_t cache_bit) 95 { 96 uint32_t reg; 97 98 if (cache_bit == CR_C) { 99 /* if disabling data cache, disable mmu too */ 100 cache_bit |= CR_M; 101 flush_cache(0, ~0); 102 } 103 reg = get_cr(); 104 cp_delay(); 105 set_cr(reg & ~cache_bit); 106 } 107 #endif 108 109 #ifdef CONFIG_SYS_NO_ICACHE 110 void icache_enable (void) 111 { 112 return; 113 } 114 115 void icache_disable (void) 116 { 117 return; 118 } 119 120 int icache_status (void) 121 { 122 return 0; /* always off */ 123 } 124 #else 125 void icache_enable(void) 126 { 127 cache_enable(CR_I); 128 } 129 130 void icache_disable(void) 131 { 132 cache_disable(CR_I); 133 } 134 135 int icache_status(void) 136 { 137 return (get_cr() & CR_I) != 0; 138 } 139 #endif 140 141 #ifdef CONFIG_SYS_NO_DCACHE 142 void dcache_enable (void) 143 { 144 return; 145 } 146 147 void dcache_disable (void) 148 { 149 return; 150 } 151 152 int dcache_status (void) 153 { 154 return 0; /* always off */ 155 } 156 #else 157 void dcache_enable(void) 158 { 159 cache_enable(CR_C); 160 } 161 162 void dcache_disable(void) 163 { 164 cache_disable(CR_C); 165 } 166 167 int dcache_status(void) 168 { 169 return (get_cr() & CR_C) != 0; 170 } 171 #endif 172