rockchip: rv1126: rename periph device region

Adding to whitelist.txt:
CONFIG_PERIPH_DEVICE_START_ADDR
CONFIG_PERIPH_DEVICE_END_ADDR

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id:

rockchip: rv1126: rename periph device region

Adding to whitelist.txt:
CONFIG_PERIPH_DEVICE_START_ADDR
CONFIG_PERIPH_DEVICE_END_ADDR

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia07a467489e52b7580351829768437dc67e71833

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arm: cp15: only map periph device region as dcache off for thunder-boot SPL

Don't waste time to map all 4GB region.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I24ba4e4e42545dcf3a

arm: cp15: only map periph device region as dcache off for thunder-boot SPL

Don't waste time to map all 4GB region.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I24ba4e4e42545dcf3ac6622c36995485956eae1b

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Merge branch 'next-dev' into thunder-boot

arm: shield executing arm_init_before_mmu in spl

The device do not initialize the cache and mmu in bootrom and ddr,
so the spl do not need to clear the cache and disable mmu in function
arm_init_bef

arm: shield executing arm_init_before_mmu in spl

The device do not initialize the cache and mmu in bootrom and ddr,
so the spl do not need to clear the cache and disable mmu in function
arm_init_before_mmu.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: If7b19fa762c4803dcfc58c7b16fd8236a2262729

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ARM: remove bogus cp_delay() function

The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr

ARM: remove bogus cp_delay() function

The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr() being optimised out eventually.
This has been fixed in commit 53fd4b8c22bb ("arm: mmu: Add missing volatile for reading SCTLR register")
but the bogus cp_delay() function which was introduced as a workaround
for the malfunctioning get_cr() was never removed.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>

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Merge git://git.denx.de/u-boot-dm

arm: Disable LPAE if not enabled

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does e

arm: Disable LPAE if not enabled

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
ha

arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: Rename HCTR to HTCR

This appears to be a typo. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>

arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly define

arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

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arm: print the cache config option in hex instead of decimal

Printing the option value in hex makes it more comprehensible.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@ko

arm: print the cache config option in hex instead of decimal

Printing the option value in hex makes it more comprehensible.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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arm: cache: always flush cache line size for page table

The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_

arm: cache: always flush cache line size for page table

The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

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arm: cache: add support for LPAE for region D$ behavior

Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.

Signed-

arm: cache: add support for LPAE for region D$ behavior

Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

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arm: Add support for HYP mode and LPAE page tables

We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run

arm: Add support for HYP mode and LPAE page tables

We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf <agraf@suse.de>

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arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured f

arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching mo

ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

ARM: cache-cp15: Use more accurate types

size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so u

ARM: cache-cp15: Use more accurate types

size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga

Fix a trivial conflict in dw_mmc.c after talking with Marek.

Conflicts:
drivers/mmc/dw_mmc.c

Signed-off-by: Tom Rini

Merge branch 'topic/arm/socfpga-20141006' of git://git.denx.de/u-boot-socfpga

Fix a trivial conflict in dw_mmc.c after talking with Marek.

Conflicts:
drivers/mmc/dw_mmc.c

Signed-off-by: Tom Rini <trini@ti.com>

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Merge branches 'topic/drivers/fpga-20141006', 'topic/drivers/mmc-20141006', 'topic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD

arm: cache: Add support for write-allocate D-Cache

Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .

Signed-off-

arm: cache: Add support for write-allocate D-Cache

Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

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ARM: Fix overflow in MMU setup

The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it the

ARM: Fix overflow in MMU setup

The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.

The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.

Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
boards.cfg