1*ea0364f1SPeter Tyser /* 2*ea0364f1SPeter Tyser * (C) Copyright 2002 3*ea0364f1SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*ea0364f1SPeter Tyser * 5*ea0364f1SPeter Tyser * See file CREDITS for list of people who contributed to this 6*ea0364f1SPeter Tyser * project. 7*ea0364f1SPeter Tyser * 8*ea0364f1SPeter Tyser * This program is free software; you can redistribute it and/or 9*ea0364f1SPeter Tyser * modify it under the terms of the GNU General Public License as 10*ea0364f1SPeter Tyser * published by the Free Software Foundation; either version 2 of 11*ea0364f1SPeter Tyser * the License, or (at your option) any later version. 12*ea0364f1SPeter Tyser * 13*ea0364f1SPeter Tyser * This program is distributed in the hope that it will be useful, 14*ea0364f1SPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*ea0364f1SPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*ea0364f1SPeter Tyser * GNU General Public License for more details. 17*ea0364f1SPeter Tyser * 18*ea0364f1SPeter Tyser * You should have received a copy of the GNU General Public License 19*ea0364f1SPeter Tyser * along with this program; if not, write to the Free Software 20*ea0364f1SPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*ea0364f1SPeter Tyser * MA 02111-1307 USA 22*ea0364f1SPeter Tyser */ 23*ea0364f1SPeter Tyser 24*ea0364f1SPeter Tyser #include <common.h> 25*ea0364f1SPeter Tyser #include <asm/system.h> 26*ea0364f1SPeter Tyser 27*ea0364f1SPeter Tyser #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) 28*ea0364f1SPeter Tyser static void cp_delay (void) 29*ea0364f1SPeter Tyser { 30*ea0364f1SPeter Tyser volatile int i; 31*ea0364f1SPeter Tyser 32*ea0364f1SPeter Tyser /* copro seems to need some delay between reading and writing */ 33*ea0364f1SPeter Tyser for (i = 0; i < 100; i++) 34*ea0364f1SPeter Tyser nop(); 35*ea0364f1SPeter Tyser } 36*ea0364f1SPeter Tyser 37*ea0364f1SPeter Tyser /* cache_bit must be either CR_I or CR_C */ 38*ea0364f1SPeter Tyser static void cache_enable(uint32_t cache_bit) 39*ea0364f1SPeter Tyser { 40*ea0364f1SPeter Tyser uint32_t reg; 41*ea0364f1SPeter Tyser 42*ea0364f1SPeter Tyser reg = get_cr(); /* get control reg. */ 43*ea0364f1SPeter Tyser cp_delay(); 44*ea0364f1SPeter Tyser set_cr(reg | cache_bit); 45*ea0364f1SPeter Tyser } 46*ea0364f1SPeter Tyser 47*ea0364f1SPeter Tyser /* cache_bit must be either CR_I or CR_C */ 48*ea0364f1SPeter Tyser static void cache_disable(uint32_t cache_bit) 49*ea0364f1SPeter Tyser { 50*ea0364f1SPeter Tyser uint32_t reg; 51*ea0364f1SPeter Tyser 52*ea0364f1SPeter Tyser reg = get_cr(); 53*ea0364f1SPeter Tyser cp_delay(); 54*ea0364f1SPeter Tyser set_cr(reg & ~cache_bit); 55*ea0364f1SPeter Tyser } 56*ea0364f1SPeter Tyser #endif 57*ea0364f1SPeter Tyser 58*ea0364f1SPeter Tyser #ifdef CONFIG_SYS_NO_ICACHE 59*ea0364f1SPeter Tyser void icache_enable (void) 60*ea0364f1SPeter Tyser { 61*ea0364f1SPeter Tyser return; 62*ea0364f1SPeter Tyser } 63*ea0364f1SPeter Tyser 64*ea0364f1SPeter Tyser void icache_disable (void) 65*ea0364f1SPeter Tyser { 66*ea0364f1SPeter Tyser return; 67*ea0364f1SPeter Tyser } 68*ea0364f1SPeter Tyser 69*ea0364f1SPeter Tyser int icache_status (void) 70*ea0364f1SPeter Tyser { 71*ea0364f1SPeter Tyser return 0; /* always off */ 72*ea0364f1SPeter Tyser } 73*ea0364f1SPeter Tyser #else 74*ea0364f1SPeter Tyser void icache_enable(void) 75*ea0364f1SPeter Tyser { 76*ea0364f1SPeter Tyser cache_enable(CR_I); 77*ea0364f1SPeter Tyser } 78*ea0364f1SPeter Tyser 79*ea0364f1SPeter Tyser void icache_disable(void) 80*ea0364f1SPeter Tyser { 81*ea0364f1SPeter Tyser cache_disable(CR_I); 82*ea0364f1SPeter Tyser } 83*ea0364f1SPeter Tyser 84*ea0364f1SPeter Tyser int icache_status(void) 85*ea0364f1SPeter Tyser { 86*ea0364f1SPeter Tyser return (get_cr() & CR_I) != 0; 87*ea0364f1SPeter Tyser } 88*ea0364f1SPeter Tyser #endif 89*ea0364f1SPeter Tyser 90*ea0364f1SPeter Tyser #ifdef CONFIG_SYS_NO_DCACHE 91*ea0364f1SPeter Tyser void dcache_enable (void) 92*ea0364f1SPeter Tyser { 93*ea0364f1SPeter Tyser return; 94*ea0364f1SPeter Tyser } 95*ea0364f1SPeter Tyser 96*ea0364f1SPeter Tyser void dcache_disable (void) 97*ea0364f1SPeter Tyser { 98*ea0364f1SPeter Tyser return; 99*ea0364f1SPeter Tyser } 100*ea0364f1SPeter Tyser 101*ea0364f1SPeter Tyser int dcache_status (void) 102*ea0364f1SPeter Tyser { 103*ea0364f1SPeter Tyser return 0; /* always off */ 104*ea0364f1SPeter Tyser } 105*ea0364f1SPeter Tyser #else 106*ea0364f1SPeter Tyser void dcache_enable(void) 107*ea0364f1SPeter Tyser { 108*ea0364f1SPeter Tyser cache_enable(CR_C); 109*ea0364f1SPeter Tyser } 110*ea0364f1SPeter Tyser 111*ea0364f1SPeter Tyser void dcache_disable(void) 112*ea0364f1SPeter Tyser { 113*ea0364f1SPeter Tyser cache_disable(CR_C); 114*ea0364f1SPeter Tyser } 115*ea0364f1SPeter Tyser 116*ea0364f1SPeter Tyser int dcache_status(void) 117*ea0364f1SPeter Tyser { 118*ea0364f1SPeter Tyser return (get_cr() & CR_C) != 0; 119*ea0364f1SPeter Tyser } 120*ea0364f1SPeter Tyser #endif 121