1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_SHARE_H 7 #define _ASM_ARCH_SDRAM_SHARE_H 8 9 #ifndef MHZ 10 #define MHZ (1000 * 1000) 11 #endif 12 13 #define PATTERN (0x5aa5f00f) 14 15 #define MIN(a, b) (((a) > (b)) ? (b) : (a)) 16 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 17 18 /* get head info for initial */ 19 #define DDR_FREQ_F0_SHIFT (0) 20 #define DDR_FREQ_F1_SHIFT (12) 21 #define DDR_FREQ_F2_SHIFT (0) 22 #define DDR_FREQ_F3_SHIFT (12) 23 #define DDR_FREQ_F4_SHIFT (0) 24 #define DDR_FREQ_F5_SHIFT (12) 25 #define DDR_FREQ_MASK (0xfff) 26 27 #define UART_INFO_ID_SHIFT (28) 28 #define UART_INFO_IOMUX_SHIFT (24) 29 #define UART_INFO_BAUD_SHIFT (0) 30 #define UART_INFO_ID(n) (((n) >> 28) & 0xf) 31 #define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf) 32 #define UART_INFO_BAUD(n) ((n) & 0xffffff) 33 34 /* g_ch_info[15:0]: g_stdby_idle */ 35 #define STANDBY_IDLE(n) ((n) & 0xffff) 36 37 #define SR_INFO(n) (((n) >> 16) & 0xffff) 38 #define PD_INFO(n) ((n) & 0xffff) 39 40 #define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf) 41 #define CHANNEL_MASK(n) (((n) >> 24) & 0xf) 42 #define STRIDE_TYPE(n) (((n) >> 16) & 0xff) 43 44 #define DDR_2T_INFO(n) ((n) & 1) 45 #define SSMOD_SPREAD(n) (((n) >> 1) & 0x1f) 46 #define SSMOD_DIV(n) (((n) >> 6) & 0xf) 47 #define SSMOD_DOWNSPREAD(n) (((n) >> 10) & 0x1) 48 49 /* sdram_head_info_v2 define */ 50 /* for *_drv_odten and *_drv_odtoff */ 51 #define PHY_DQ_DRV_SHIFT 0 52 #define PHY_CA_DRV_SHIFT 8 53 #define PHY_CLK_DRV_SHIFT 16 54 #define DRAM_DQ_DRV_SHIFT 24 55 #define DRV_INFO_PHY_DQ_DRV(n) ((n) & 0xff) 56 #define DRV_INFO_PHY_CA_DRV(n) (((n) >> PHY_CA_DRV_SHIFT) & 0xff) 57 #define DRV_INFO_PHY_CLK_DRV(n) (((n) >> PHY_CLK_DRV_SHIFT) & 0xff) 58 #define DRV_INFO_DRAM_DQ_DRV(n) (((n) >> DRAM_DQ_DRV_SHIFT) & 0xff) 59 60 /* for *_odt_info */ 61 #define DRAM_ODT_SHIFT 0 62 #define PHY_ODT_SHIFT 8 63 #define PHY_ODT_PUUP_EN_SHIFT 18 64 #define PHY_ODT_PUDN_EN_SHIFT 19 65 #define ODT_INFO_DRAM_ODT(n) (((n) >> DRAM_ODT_SHIFT) & 0xff) 66 #define ODT_INFO_PHY_ODT(n) (((n) >> PHY_ODT_SHIFT) & 0x3ff) 67 #define ODT_INFO_PULLUP_EN(n) (((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1) 68 #define ODT_INFO_PULLDOWN_EN(n) (((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1) 69 70 /* for *odt_en_freq; */ 71 #define DRAM_ODT_EN_FREQ_SHIFT 0 72 #define PHY_ODT_EN_FREQ_SHIFT 12 73 #define DRAMODT_EN_FREQ(n) (((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \ 74 0xfff) 75 #define PHYODT_EN_FREQ(n) (((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff) 76 77 #define PHY_DQ_SR_SHIFT 0 78 #define PHY_CA_SR_SHIFT 8 79 #define PHY_CLK_SR_SHIFT 16 80 #define DQ_SR_INFO(n) (((n) >> PHY_DQ_SR_SHIFT) & 0xff) 81 #define CA_SR_INFO(n) (((n) >> PHY_CA_SR_SHIFT) & 0xff) 82 #define CLK_SR_INFO(n) (((n) >> PHY_CLK_SR_SHIFT) & 0xff) 83 84 /* LP4 */ 85 #define LP4_CA_ODT_SHIFT (18) 86 #define LP4_DRV_PU_CAL_ODTEN_SHIFT (26) 87 #define LP4_DRV_PU_CAL_ODTOFF_SHIFT (27) 88 #define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT (28) 89 #define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT (29) 90 #define ODT_INFO_LP4_CA_ODT(n) (((n) >> LP4_CA_ODT_SHIFT) & \ 91 0xff) 92 #define LP4_DRV_PU_CAL_ODTEN(n) \ 93 (((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1) 94 #define LP4_DRV_PU_CAL_ODTOFF(n) \ 95 (((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1) 96 #define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n) \ 97 (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1) 98 #define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n) \ 99 (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1) 100 101 #define PHY_LP4_CS_DRV_ODTEN_SHIFT (0) 102 #define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8) 103 #define LP4_ODTE_CK_SHIFT (16) 104 #define LP4_ODTE_CS_EN_SHIFT (17) 105 #define LP4_ODTD_CA_EN_SHIFT (18) 106 #define PHY_LP4_CS_DRV_ODTEN(n) \ 107 (((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff) 108 #define PHY_LP4_CS_DRV_ODTOFF(n) \ 109 (((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff) 110 #define LP4_ODTE_CK_EN(n) (((n) >> LP4_ODTE_CK_SHIFT) & 1) 111 #define LP4_ODTE_CS_EN(n) (((n) >> LP4_ODTE_CS_EN_SHIFT) & 1) 112 #define LP4_ODTD_CA_EN(n) (((n) >> LP4_ODTD_CA_EN_SHIFT) & 1) 113 114 #define PHY_LP4_DQ_VREF_SHIFT (0) 115 #define LP4_DQ_VREF_SHIFT (10) 116 #define LP4_CA_VREF_SHIFT (20) 117 118 #define PHY_LP4_DQ_VREF(n) \ 119 (((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff) 120 #define LP4_DQ_VREF(n) (((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff) 121 #define LP4_CA_VREF(n) (((n) >> LP4_CA_VREF_SHIFT) & 0x3ff) 122 123 #define LP4_DQ_ODT_EN_FREQ_SHIFT (0) 124 #define PHY_LP4_ODT_EN_FREQ_SHIFT (12) 125 #define LP4_CA_ODT_EN_FREQ_SHIFT (0) 126 #define PHY_LP4_ODT_EN_FREQ(n) \ 127 (((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff) 128 #define LP4_DQ_ODT_EN_FREQ(n) \ 129 (((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff) 130 #define LP4_CA_ODT_EN_FREQ(n) \ 131 (((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff) 132 133 struct sdram_head_info_v0 { 134 u32 start_tag; 135 u32 version_info; 136 u32 gcpu_gen_freq; 137 u32 g_d2_lp2_freq; 138 u32 g_d3_lp3_freq; 139 u32 g_d4_lp4_freq; 140 u32 g_uart_info; 141 u32 g_sr_pd_idle; 142 u32 g_ch_info; 143 u32 g_2t_info; 144 u32 reserved11; 145 u32 reserved12; 146 u32 reserved13; 147 }; 148 149 struct index_info { 150 u8 offset; 151 u8 size; 152 }; 153 154 struct sdram_head_info_index_v2 { 155 u32 start_tag; 156 u32 version_info; 157 struct index_info cpu_gen_index; 158 struct index_info global_index; 159 160 struct index_info ddr2_index; 161 struct index_info ddr3_index; 162 163 struct index_info ddr4_index; 164 struct index_info ddr5_index; 165 166 struct index_info lp2_index; 167 struct index_info lp3_index; 168 169 struct index_info lp4_index; 170 struct index_info lp5_index; 171 172 struct index_info skew_index; 173 struct index_info dq_map_index; 174 175 struct index_info lp4x_index; 176 struct index_info reserved; 177 }; 178 179 struct global_info { 180 u32 uart_info; 181 u32 sr_pd_info; 182 u32 ch_info; 183 u32 info_2t; 184 u32 reserved[4]; 185 }; 186 187 struct ddr2_3_4_lp2_3_info { 188 u32 ddr_freq0_1; 189 u32 ddr_freq2_3; 190 u32 ddr_freq4_5; 191 u32 drv_when_odten; 192 u32 drv_when_odtoff; 193 u32 odt_info; 194 u32 odten_freq; 195 u32 sr_when_odten; 196 u32 sr_when_odtoff; 197 }; 198 199 struct lp4_info { 200 u32 ddr_freq0_1; 201 u32 ddr_freq2_3; 202 u32 ddr_freq4_5; 203 u32 drv_when_odten; 204 u32 drv_when_odtoff; 205 u32 odt_info; 206 u32 dq_odten_freq; 207 u32 sr_when_odten; 208 u32 sr_when_odtoff; 209 u32 ca_odten_freq; 210 u32 cs_drv_ca_odt_info; 211 u32 vref_when_odten; 212 u32 vref_when_odtoff; 213 }; 214 215 struct dq_map_info { 216 u32 byte_map[2]; 217 u32 lp3_dq0_7_map; 218 u32 lp2_dq0_7_map; 219 u32 ddr4_dq_map[4]; 220 }; 221 222 struct sdram_cap_info { 223 unsigned int rank; 224 unsigned int col; 225 /* 3:8bank, 2:4bank */ 226 unsigned int bk; 227 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 228 unsigned int bw; 229 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 230 unsigned int dbw; 231 unsigned int row_3_4; 232 unsigned int cs0_row; 233 unsigned int cs1_row; 234 #ifdef CONFIG_ROCKCHIP_RK3568 235 unsigned int cs2_row; 236 unsigned int cs3_row; 237 #endif 238 unsigned int cs0_high16bit_row; 239 unsigned int cs1_high16bit_row; 240 unsigned int ddrconfig; 241 }; 242 243 struct sdram_base_params { 244 unsigned int ddr_freq; 245 unsigned int dramtype; 246 unsigned int num_channels; 247 unsigned int stride; 248 unsigned int odt; 249 }; 250 251 /* 252 * sys_reg bitfield struct 253 * [31] row_3_4_ch1 254 * [30] row_3_4_ch0 255 * [29:28] chinfo 256 * [27] rank_ch1 257 * [26:25] col_ch1 258 * [24] bk_ch1 259 * [23:22] cs0_row_ch1 260 * [21:20] cs1_row_ch1 261 * [19:18] bw_ch1 262 * [17:16] dbw_ch1; 263 * [15:13] ddrtype 264 * [12] channelnum 265 * [11] rank_ch0 266 * [10:9] col_ch0 267 * [8] bk_ch0 268 * [7:6] cs0_row_ch0 269 * [5:4] cs1_row_ch0 270 * [3:2] bw_ch0 271 * [1:0] dbw_ch0 272 */ 273 274 #define DDR_SYS_REG_VERSION (0x2) 275 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 276 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 277 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 278 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 279 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 280 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 281 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 282 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) 283 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) 284 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) 285 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) 286 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ 287 (8 + ((ch) * 16))) 288 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) 289 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) 290 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) 291 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) 292 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) 293 /* sys reg 3 */ 294 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 295 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 296 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ 297 (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ 298 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 299 (5 + 2 * (ch)); \ 300 } while (0) 301 302 #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ 303 ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ 304 ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 305 306 #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ 307 (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ 308 (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ 309 (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ 310 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 311 (4 + 2 * (ch)); \ 312 } while (0) 313 314 #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ 315 ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ 316 ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 317 318 #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) 319 #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) 320 321 void sdram_org_config(struct sdram_cap_info *cap_info, 322 struct sdram_base_params *base, 323 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 324 325 int sdram_detect_bw(struct sdram_cap_info *cap_info); 326 int sdram_detect_cs(struct sdram_cap_info *cap_info); 327 int sdram_detect_col(struct sdram_cap_info *cap_info, 328 u32 coltmp); 329 int sdram_detect_bank(struct sdram_cap_info *cap_info, 330 u32 coltmp, u32 bktmp); 331 int sdram_detect_bg(struct sdram_cap_info *cap_info, 332 u32 coltmp); 333 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); 334 int sdram_detect_row(struct sdram_cap_info *cap_info, 335 u32 coltmp, u32 bktmp, u32 rowtmp); 336 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, 337 u32 coltmp, u32 bktmp); 338 int sdram_detect_high_row(struct sdram_cap_info *cap_info); 339 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); 340 341 void sdram_print_dram_type(unsigned char dramtype); 342 void sdram_print_ddr_info(struct sdram_cap_info *cap_info, 343 struct sdram_base_params *base, u32 split); 344 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); 345 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); 346 347 #endif 348