1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_SHARE_H 7 #define _ASM_ARCH_SDRAM_SHARE_H 8 9 #ifndef MHZ 10 #define MHZ (1000 * 1000) 11 #endif 12 13 #define PATTERN (0x5aa5f00f) 14 15 #define MIN(a, b) (((a) > (b)) ? (b) : (a)) 16 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 17 18 struct sdram_cap_info { 19 unsigned int rank; 20 unsigned int col; 21 /* 3:8bank, 2:4bank */ 22 unsigned int bk; 23 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 24 unsigned int bw; 25 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 26 unsigned int dbw; 27 unsigned int row_3_4; 28 unsigned int cs0_row; 29 unsigned int cs1_row; 30 unsigned int cs0_high16bit_row; 31 unsigned int cs1_high16bit_row; 32 unsigned int ddrconfig; 33 }; 34 35 struct sdram_base_params { 36 unsigned int ddr_freq; 37 unsigned int dramtype; 38 unsigned int num_channels; 39 unsigned int stride; 40 unsigned int odt; 41 }; 42 43 /* 44 * sys_reg bitfield struct 45 * [31] row_3_4_ch1 46 * [30] row_3_4_ch0 47 * [29:28] chinfo 48 * [27] rank_ch1 49 * [26:25] col_ch1 50 * [24] bk_ch1 51 * [23:22] cs0_row_ch1 52 * [21:20] cs1_row_ch1 53 * [19:18] bw_ch1 54 * [17:16] dbw_ch1; 55 * [15:13] ddrtype 56 * [12] channelnum 57 * [11] rank_ch0 58 * [10:9] col_ch0 59 * [8] bk_ch0 60 * [7:6] cs0_row_ch0 61 * [5:4] cs1_row_ch0 62 * [3:2] bw_ch0 63 * [1:0] dbw_ch0 64 */ 65 66 #define DDR_SYS_REG_VERSION (0x2) 67 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 68 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 69 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 70 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 71 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 72 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 73 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 74 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) 75 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) 76 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) 77 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) 78 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ 79 (8 + ((ch) * 16))) 80 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) 81 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) 82 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) 83 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) 84 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) 85 /* sys reg 3 */ 86 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 87 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 88 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ 89 (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ 90 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 91 (5 + 2 * (ch)); \ 92 } while (0) 93 94 #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ 95 ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ 96 ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 97 98 #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ 99 (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ 100 (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ 101 (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ 102 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 103 (4 + 2 * (ch)); \ 104 } while (0) 105 106 #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ 107 ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ 108 ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 109 110 #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) 111 #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) 112 113 void sdram_org_config(struct sdram_cap_info *cap_info, 114 struct sdram_base_params *base, 115 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 116 117 int sdram_detect_bw(struct sdram_cap_info *cap_info); 118 int sdram_detect_cs(struct sdram_cap_info *cap_info); 119 int sdram_detect_col(struct sdram_cap_info *cap_info, 120 u32 coltmp); 121 int sdram_detect_bank(struct sdram_cap_info *cap_info, 122 u32 coltmp, u32 bktmp); 123 int sdram_detect_bg(struct sdram_cap_info *cap_info, 124 u32 coltmp); 125 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); 126 int sdram_detect_row(struct sdram_cap_info *cap_info, 127 u32 coltmp, u32 bktmp, u32 rowtmp); 128 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, 129 u32 coltmp, u32 bktmp); 130 int sdram_detect_high_row(struct sdram_cap_info *cap_info); 131 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); 132 133 void sdram_print_dram_type(unsigned char dramtype); 134 void sdram_print_ddr_info(struct sdram_cap_info *cap_info, 135 struct sdram_base_params *base, u32 split); 136 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); 137 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); 138 139 #endif 140