1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_SHARE_H 7 #define _ASM_ARCH_SDRAM_SHARE_H 8 9 #define MHZ (1000000) 10 #define PATTERN (0x5aa5f00f) 11 12 struct sdram_cap_info { 13 unsigned int rank; 14 unsigned int col; 15 /* 3:8bank, 2:4bank */ 16 unsigned int bk; 17 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 18 unsigned int bw; 19 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 20 unsigned int dbw; 21 unsigned int row_3_4; 22 unsigned int cs0_row; 23 unsigned int cs1_row; 24 unsigned int cs0_high16bit_row; 25 unsigned int cs1_high16bit_row; 26 unsigned int ddrconfig; 27 }; 28 29 struct sdram_base_params { 30 unsigned int ddr_freq; 31 unsigned int dramtype; 32 unsigned int num_channels; 33 unsigned int stride; 34 unsigned int odt; 35 }; 36 37 /* 38 * sys_reg bitfield struct 39 * [31] row_3_4_ch1 40 * [30] row_3_4_ch0 41 * [29:28] chinfo 42 * [27] rank_ch1 43 * [26:25] col_ch1 44 * [24] bk_ch1 45 * [23:22] cs0_row_ch1 46 * [21:20] cs1_row_ch1 47 * [19:18] bw_ch1 48 * [17:16] dbw_ch1; 49 * [15:13] ddrtype 50 * [12] channelnum 51 * [11] rank_ch0 52 * [10:9] col_ch0 53 * [8] bk_ch0 54 * [7:6] cs0_row_ch0 55 * [5:4] cs1_row_ch0 56 * [3:2] bw_ch0 57 * [1:0] dbw_ch0 58 */ 59 60 #define DDR_SYS_REG_VERSION (0x2) 61 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 62 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 63 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 64 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 65 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 66 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 67 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 68 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) 69 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) 70 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) 71 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) 72 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ 73 (8 + ((ch) * 16))) 74 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) 75 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) 76 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) 77 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) 78 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) 79 /* sys reg 3 */ 80 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 81 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 82 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ 83 (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ 84 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 85 (5 + 2 * (ch)); \ 86 } while (0) 87 88 #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ 89 ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ 90 ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 91 92 #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ 93 (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ 94 (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ 95 (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ 96 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 97 (4 + 2 * (ch)); \ 98 } while (0) 99 100 #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ 101 ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ 102 ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 103 104 #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) 105 #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) 106 107 void sdram_org_config(struct sdram_cap_info *cap_info, 108 struct sdram_base_params *base, 109 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 110 111 int sdram_detect_bw(struct sdram_cap_info *cap_info); 112 int sdram_detect_cs(struct sdram_cap_info *cap_info); 113 int sdram_detect_col(struct sdram_cap_info *cap_info, 114 u32 coltmp); 115 int sdram_detect_bank(struct sdram_cap_info *cap_info, 116 u32 coltmp, u32 bktmp); 117 int sdram_detect_bg(struct sdram_cap_info *cap_info, 118 u32 coltmp); 119 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); 120 int sdram_detect_row(struct sdram_cap_info *cap_info, 121 u32 coltmp, u32 bktmp, u32 rowtmp); 122 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, 123 u32 coltmp, u32 bktmp); 124 int sdram_detect_high_row(struct sdram_cap_info *cap_info); 125 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); 126 127 void sdram_print_dram_type(unsigned char dramtype); 128 void sdram_print_ddr_info(struct sdram_cap_info *cap_info, 129 struct sdram_base_params *base, u32 split); 130 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); 131 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); 132 133 #endif 134