1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1126_H 8 #define _ASM_ARCH_CRU_RV1126_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #define APLL_HZ (1008 * MHz) 17 #define GPLL_HZ (1188 * MHz) 18 #define CPLL_HZ (500 * MHz) 19 #define HPLL_HZ (1400 * MHz) 20 #define PCLK_PDPMU_HZ (100 * MHz) 21 #define ACLK_PDBUS_HZ (500 * MHz) 22 #define HCLK_PDBUS_HZ (200 * MHz) 23 #define PCLK_PDBUS_HZ (100 * MHz) 24 #define ACLK_PDPHP_HZ (300 * MHz) 25 #define HCLK_PDPHP_HZ (200 * MHz) 26 #define HCLK_PDCORE_HZ (200 * MHz) 27 #define HCLK_PDAUDIO_HZ (150 * MHz) 28 #define CLK_OSC0_DIV_HZ (32768) 29 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 30 #define ACLK_PDVI_HZ (500 * MHz) 31 #define CLK_ISP_HZ (500 * MHz) 32 #define ACLK_PDISPP_HZ (500 * MHz) 33 #define CLK_ISPP_HZ (400 * MHz) 34 #define ACLK_VOP_HZ (300 * MHz) 35 #define DCLK_VOP_HZ (65 * MHz) 36 #endif 37 38 /* RV1126 pll id */ 39 enum rv1126_pll_id { 40 APLL, 41 DPLL, 42 CPLL, 43 HPLL, 44 GPLL, 45 PLL_COUNT, 46 }; 47 48 struct rv1126_clk_info { 49 unsigned long id; 50 char *name; 51 bool is_cru; 52 }; 53 54 /* Private data for the clock driver - used by rockchip_get_cru() */ 55 struct rv1126_pmuclk_priv { 56 struct rv1126_pmucru *pmucru; 57 ulong gpll_hz; 58 }; 59 60 struct rv1126_clk_priv { 61 struct rv1126_cru *cru; 62 struct rv1126_grf *grf; 63 ulong gpll_hz; 64 ulong cpll_hz; 65 ulong hpll_hz; 66 ulong armclk_hz; 67 ulong armclk_enter_hz; 68 ulong armclk_init_hz; 69 bool sync_kernel; 70 bool set_armclk_rate; 71 }; 72 73 struct rv1126_pll { 74 unsigned int con0; 75 unsigned int con1; 76 unsigned int con2; 77 unsigned int con3; 78 unsigned int con4; 79 unsigned int con5; 80 unsigned int con6; 81 unsigned int reserved0[1]; 82 }; 83 84 struct rv1126_pmucru { 85 unsigned int pmu_mode; 86 unsigned int reserved1[3]; 87 struct rv1126_pll pll; 88 unsigned int offsetcal_status; 89 unsigned int reserved2[51]; 90 unsigned int pmu_clksel_con[14]; 91 unsigned int reserved3[18]; 92 unsigned int pmu_clkgate_con[3]; 93 unsigned int reserved4[29]; 94 unsigned int pmu_softrst_con[2]; 95 unsigned int reserved5[14]; 96 unsigned int pmu_autocs_con[2]; 97 }; 98 99 check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); 100 101 struct rv1126_cru { 102 struct rv1126_pll pll[4]; 103 unsigned int offsetcal_status[4]; 104 unsigned int mode; 105 unsigned int reserved1[27]; 106 unsigned int clksel_con[78]; 107 unsigned int reserved2[18]; 108 unsigned int clkgate_con[25]; 109 unsigned int reserved3[7]; 110 unsigned int softrst_con[15]; 111 unsigned int reserved4[17]; 112 unsigned int ssgtbl[32]; 113 unsigned int glb_cnt_th; 114 unsigned int glb_rst_st; 115 unsigned int glb_srst_fst; 116 unsigned int glb_srst_snd; 117 unsigned int glb_rst_con; 118 unsigned int reserved5[11]; 119 unsigned int sdmmc_con[2]; 120 unsigned int sdio_con[2]; 121 unsigned int emmc_con[2]; 122 unsigned int reserved6[2]; 123 unsigned int gmac_con; 124 unsigned int misc[2]; 125 unsigned int reserved7[45]; 126 unsigned int autocs_con[26]; 127 }; 128 129 check_member(rv1126_cru, autocs_con[25], 0x584); 130 131 struct pll_rate_table { 132 unsigned long rate; 133 unsigned int fbdiv; 134 unsigned int postdiv1; 135 unsigned int refdiv; 136 unsigned int postdiv2; 137 unsigned int dsmpd; 138 unsigned int frac; 139 }; 140 141 struct cpu_rate_table { 142 unsigned long rate; 143 unsigned int aclk_div; 144 unsigned int pclk_div; 145 }; 146 147 #define RV1126_PMU_MODE 0x0 148 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 149 #define RV1126_PLL_CON(x) ((x) * 0x4) 150 #define RV1126_MODE_CON 0x90 151 152 enum { 153 /* CRU_PMU_CLK_SEL0_CON */ 154 RTC32K_SEL_SHIFT = 7, 155 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 156 RTC32K_SEL_PMUPVTM = 0, 157 RTC32K_SEL_OSC1_32K, 158 RTC32K_SEL_OSC0_DIV32K, 159 160 /* CRU_PMU_CLK_SEL1_CON */ 161 PCLK_PDPMU_DIV_SHIFT = 0, 162 PCLK_PDPMU_DIV_MASK = 0x1f, 163 164 /* CRU_PMU_CLK_SEL2_CON */ 165 CLK_I2C0_DIV_SHIFT = 0, 166 CLK_I2C0_DIV_MASK = 0x7f, 167 168 /* CRU_PMU_CLK_SEL3_CON */ 169 CLK_I2C2_DIV_SHIFT = 0, 170 CLK_I2C2_DIV_MASK = 0x7f, 171 172 /* CRU_PMU_CLK_SEL6_CON */ 173 CLK_PWM1_SEL_SHIFT = 15, 174 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 175 CLK_PWM1_SEL_XIN24M = 0, 176 CLK_PWM1_SEL_GPLL, 177 CLK_PWM1_DIV_SHIFT = 8, 178 CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, 179 CLK_PWM0_SEL_SHIFT = 7, 180 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 181 CLK_PWM0_SEL_XIN24M = 0, 182 CLK_PWM0_SEL_GPLL, 183 CLK_PWM0_DIV_SHIFT = 0, 184 CLK_PWM0_DIV_MASK = 0x7f, 185 186 /* CRU_PMU_CLK_SEL9_CON */ 187 CLK_SPI0_SEL_SHIFT = 7, 188 CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, 189 CLK_SPI0_SEL_GPLL = 0, 190 CLK_SPI0_SEL_XIN24M, 191 CLK_SPI0_DIV_SHIFT = 0, 192 CLK_SPI0_DIV_MASK = 0x7f, 193 194 /* CRU_PMU_CLK_SEL13_CON */ 195 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 196 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 197 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 198 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 199 200 /* CRU_CLK_SEL0_CON */ 201 CORE_HCLK_DIV_SHIFT = 8, 202 CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, 203 204 /* CRU_CLK_SEL1_CON */ 205 CORE_ACLK_DIV_SHIFT = 4, 206 CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, 207 CORE_DBG_DIV_SHIFT = 0, 208 CORE_DBG_DIV_MASK = 0x7, 209 210 /* CRU_CLK_SEL2_CON */ 211 HCLK_PDBUS_SEL_SHIFT = 15, 212 HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, 213 HCLK_PDBUS_SEL_GPLL = 0, 214 HCLK_PDBUS_SEL_CPLL, 215 HCLK_PDBUS_DIV_SHIFT = 8, 216 HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, 217 ACLK_PDBUS_SEL_SHIFT = 6, 218 ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, 219 ACLK_PDBUS_SEL_GPLL = 0, 220 ACLK_PDBUS_SEL_CPLL, 221 ACLK_PDBUS_SEL_DPLL, 222 ACLK_PDBUS_DIV_SHIFT = 0, 223 ACLK_PDBUS_DIV_MASK = 0x1f, 224 225 /* CRU_CLK_SEL3_CON */ 226 CLK_SCR1_SEL_SHIFT = 15, 227 CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, 228 CLK_SCR1_SEL_GPLL = 0, 229 CLK_SCR1_SEL_CPLL, 230 CLK_SCR1_DIV_SHIFT = 8, 231 CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, 232 PCLK_PDBUS_SEL_SHIFT = 7, 233 PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, 234 PCLK_PDBUS_SEL_GPLL = 0, 235 PCLK_PDBUS_SEL_CPLL, 236 PCLK_PDBUS_DIV_SHIFT = 0, 237 PCLK_PDBUS_DIV_MASK = 0x1f, 238 239 /* CRU_CLK_SEL4_CON */ 240 ACLK_CRYPTO_SEL_SHIFT = 7, 241 ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, 242 ACLK_CRYPTO_SEL_GPLL = 0, 243 ACLK_CRYPTO_SEL_CPLL, 244 ACLK_CRYPTO_DIV_SHIFT = 0, 245 ACLK_CRYPTO_DIV_MASK = 0x1f, 246 247 /* CRU_CLK_SEL5_CON */ 248 CLK_I2C3_DIV_SHIFT = 8, 249 CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, 250 CLK_I2C1_DIV_SHIFT = 0, 251 CLK_I2C1_DIV_MASK = 0x7f, 252 253 /* CRU_CLK_SEL6_CON */ 254 CLK_I2C5_DIV_SHIFT = 8, 255 CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, 256 CLK_I2C4_DIV_SHIFT = 0, 257 CLK_I2C4_DIV_MASK = 0x7f, 258 259 /* CRU_CLK_SEL7_CON */ 260 CLK_CRYPTO_PKA_SEL_SHIFT = 15, 261 CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, 262 CLK_CRYPTO_PKA_SEL_GPLL = 0, 263 CLK_CRYPTO_PKA_SEL_CPLL, 264 CLK_CRYPTO_PKA_DIV_SHIFT = 8, 265 CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, 266 CLK_CRYPTO_CORE_SEL_SHIFT = 7, 267 CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, 268 CLK_CRYPTO_CORE_SEL_GPLL = 0, 269 CLK_CRYPTO_CORE_SEL_CPLL, 270 CLK_CRYPTO_CORE_DIV_SHIFT = 0, 271 CLK_CRYPTO_CORE_DIV_MASK = 0x1f, 272 273 /* CRU_CLK_SEL8_CON */ 274 CLK_SPI1_SEL_SHIFT = 8, 275 CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, 276 CLK_SPI1_SEL_GPLL = 0, 277 CLK_SPI1_SEL_XIN24M, 278 CLK_SPI1_DIV_SHIFT = 0, 279 CLK_SPI1_DIV_MASK = 0x7f, 280 281 /* CRU_CLK_SEL9_CON */ 282 CLK_PWM2_SEL_SHIFT = 15, 283 CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 284 CLK_PWM2_SEL_XIN24M = 0, 285 CLK_PWM2_SEL_GPLL, 286 CLK_PWM2_DIV_SHIFT = 8, 287 CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, 288 289 /* CRU_CLK_SEL20_CON */ 290 CLK_SARADC_DIV_SHIFT = 0, 291 CLK_SARADC_DIV_MASK = 0x7ff, 292 293 #ifdef CONFIG_SPL_BUILD 294 /* CRU_CLK_SEL25_CON */ 295 DCLK_DECOM_SEL_SHIFT = 15, 296 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 297 DCLK_DECOM_SEL_GPLL = 0, 298 DCLK_DECOM_SEL_CPLL, 299 DCLK_DECOM_DIV_SHIFT = 8, 300 DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT, 301 #endif 302 303 /* CRU_CLK_SEL26_CON */ 304 HCLK_PDAUDIO_DIV_SHIFT = 0, 305 HCLK_PDAUDIO_DIV_MASK = 0x1f, 306 307 /* CRU_CLK_SEL45_CON */ 308 ACLK_PDVO_SEL_SHIFT = 7, 309 ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, 310 ACLK_PDVO_SEL_GPLL = 0, 311 ACLK_PDVO_SEL_CPLL, 312 ACLK_PDVO_DIV_SHIFT = 0, 313 ACLK_PDVO_DIV_MASK = 0x1f, 314 315 /* CRU_CLK_SEL47_CON */ 316 DCLK_VOP_SEL_SHIFT = 8, 317 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 318 DCLK_VOP_SEL_GPLL = 0, 319 DCLK_VOP_SEL_CPLL, 320 DCLK_VOP_DIV_SHIFT = 0, 321 DCLK_VOP_DIV_MASK = 0xff, 322 323 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 324 /* CRU_CLK_SEL49_CON */ 325 ACLK_PDVI_SEL_SHIFT = 6, 326 ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, 327 ACLK_PDVI_SEL_CPLL = 0, 328 ACLK_PDVI_SEL_GPLL, 329 ACLK_PDVI_SEL_HPLL, 330 ACLK_PDVI_DIV_SHIFT = 0, 331 ACLK_PDVI_DIV_MASK = 0x1f, 332 333 /* CRU_CLK_SEL50_CON */ 334 CLK_ISP_SEL_SHIFT = 6, 335 CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT, 336 CLK_ISP_SEL_GPLL = 0, 337 CLK_ISP_SEL_CPLL, 338 CLK_ISP_SEL_HPLL, 339 CLK_ISP_DIV_SHIFT = 0, 340 CLK_ISP_DIV_MASK = 0x1f, 341 #endif 342 343 /* CRU_CLK_SEL53_CON */ 344 HCLK_PDPHP_DIV_SHIFT = 8, 345 HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, 346 ACLK_PDPHP_SEL_SHIFT = 7, 347 ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, 348 ACLK_PDPHP_SEL_GPLL = 0, 349 ACLK_PDPHP_SEL_CPLL, 350 ACLK_PDPHP_DIV_SHIFT = 0, 351 ACLK_PDPHP_DIV_MASK = 0x1f, 352 353 /* CRU_CLK_SEL57_CON */ 354 EMMC_SEL_SHIFT = 14, 355 EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, 356 EMMC_SEL_GPLL = 0, 357 EMMC_SEL_CPLL, 358 EMMC_SEL_XIN24M, 359 EMMC_DIV_SHIFT = 0, 360 EMMC_DIV_MASK = 0xff, 361 362 /* CRU_CLK_SEL58_CON */ 363 SCLK_SFC_SEL_SHIFT = 15, 364 SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, 365 SCLK_SFC_SEL_CPLL = 0, 366 SCLK_SFC_SEL_GPLL, 367 SCLK_SFC_DIV_SHIFT = 0, 368 SCLK_SFC_DIV_MASK = 0xff, 369 370 /* CRU_CLK_SEL59_CON */ 371 CLK_NANDC_SEL_SHIFT = 15, 372 CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, 373 CLK_NANDC_SEL_GPLL = 0, 374 CLK_NANDC_SEL_CPLL, 375 CLK_NANDC_DIV_SHIFT = 0, 376 CLK_NANDC_DIV_MASK = 0xff, 377 378 /* CRU_CLK_SEL61_CON */ 379 CLK_GMAC_OUT_SEL_SHIFT = 15, 380 CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT, 381 CLK_GMAC_OUT_SEL_CPLL = 0, 382 CLK_GMAC_OUT_SEL_GPLL, 383 CLK_GMAC_OUT_DIV_SHIFT = 8, 384 CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT, 385 386 /* CRU_CLK_SEL63_CON */ 387 PCLK_GMAC_DIV_SHIFT = 8, 388 PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT, 389 CLK_GMAC_SRC_SEL_SHIFT = 7, 390 CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT, 391 CLK_GMAC_SRC_SEL_CPLL = 0, 392 CLK_GMAC_SRC_SEL_GPLL, 393 CLK_GMAC_SRC_DIV_SHIFT = 0, 394 CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, 395 396 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 397 /* CRU_CLK_SEL68_CON */ 398 ACLK_PDISPP_SEL_SHIFT = 6, 399 ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, 400 ACLK_PDISPP_SEL_CPLL = 0, 401 ACLK_PDISPP_SEL_GPLL, 402 ACLK_PDISPP_SEL_HPLL, 403 ACLK_PDISPP_DIV_SHIFT = 0, 404 ACLK_PDISPP_DIV_MASK = 0x1f, 405 406 /* CRU_CLK_SEL69_CON */ 407 CLK_ISPP_SEL_SHIFT = 6, 408 CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT, 409 CLK_ISPP_SEL_CPLL = 0, 410 CLK_ISPP_SEL_GPLL, 411 CLK_ISPP_SEL_HPLL, 412 CLK_ISPP_DIV_SHIFT = 0, 413 CLK_ISPP_DIV_MASK = 0x1f, 414 #endif 415 416 /* CRU_GMAC_CON */ 417 GMAC_SRC_M1_SEL_SHIFT = 5, 418 GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, 419 GMAC_SRC_M1_SEL_INT = 0, 420 GMAC_SRC_M1_SEL_EXT, 421 GMAC_MODE_SEL_SHIFT = 4, 422 GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT, 423 GMAC_RGMII_MODE = 0, 424 GMAC_RMII_MODE, 425 RGMII_CLK_SEL_SHIFT = 2, 426 RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT, 427 RGMII_CLK_DIV0 = 0, 428 RGMII_CLK_DIV1, 429 RGMII_CLK_DIV50, 430 RGMII_CLK_DIV5, 431 RMII_CLK_SEL_SHIFT = 1, 432 RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, 433 RMII_CLK_DIV20 = 0, 434 RMII_CLK_DIV2, 435 GMAC_SRC_M0_SEL_SHIFT = 0, 436 GMAC_SRC_M0_SEL_MASK = 0x1, 437 GMAC_SRC_M0_SEL_INT = 0, 438 GMAC_SRC_M0_SEL_EXT, 439 440 /* GRF_IOFUNC_CON1 */ 441 GMAC_SRC_SEL_SHIFT = 12, 442 GMAC_SRC_SEL_MASK = 1 < GMAC_SRC_SEL_SHIFT, 443 GMAC_SRC_SEL_M0 = 0, 444 GMAC_SRC_SEL_M1, 445 }; 446 #endif 447