1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1108_H 8 #define _ASM_ARCH_CRU_RV1108_H 9 10 #include <common.h> 11 12 #define OSC_HZ (24 * 1000 * 1000) 13 14 #define APLL_HZ (600 * 1000000) 15 #define GPLL_HZ (1188 * 1000000) 16 #define ACLK_PERI_HZ (148500000) 17 #define HCLK_PERI_HZ (148500000) 18 #define PCLK_PERI_HZ (74250000) 19 #define ACLK_BUS_HZ (148500000) 20 21 struct rv1108_clk_priv { 22 struct rv1108_cru *cru; 23 ulong rate; 24 }; 25 26 struct rv1108_cru { 27 struct rv1108_pll { 28 unsigned int con0; 29 unsigned int con1; 30 unsigned int con2; 31 unsigned int con3; 32 unsigned int con4; 33 unsigned int con5; 34 unsigned int reserved[2]; 35 } pll[3]; 36 unsigned int clksel_con[46]; 37 unsigned int reserved1[2]; 38 unsigned int clkgate_con[20]; 39 unsigned int reserved2[4]; 40 unsigned int softrst_con[13]; 41 unsigned int reserved3[3]; 42 unsigned int glb_srst_fst_val; 43 unsigned int glb_srst_snd_val; 44 unsigned int glb_cnt_th; 45 unsigned int misc_con; 46 unsigned int glb_rst_con; 47 unsigned int glb_rst_st; 48 unsigned int sdmmc_con[2]; 49 unsigned int sdio_con[2]; 50 unsigned int emmc_con[2]; 51 }; 52 check_member(rv1108_cru, emmc_con[1], 0x01ec); 53 54 struct pll_div { 55 u32 refdiv; 56 u32 fbdiv; 57 u32 postdiv1; 58 u32 postdiv2; 59 u32 frac; 60 }; 61 62 enum { 63 /* PLL CON0 */ 64 FBDIV_MASK = 0xfff, 65 FBDIV_SHIFT = 0, 66 67 /* PLL CON1 */ 68 POSTDIV2_SHIFT = 12, 69 POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, 70 POSTDIV1_SHIFT = 8, 71 POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, 72 REFDIV_MASK = 0x3f, 73 REFDIV_SHIFT = 0, 74 75 /* PLL CON2 */ 76 LOCK_STA_SHIFT = 31, 77 LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, 78 FRACDIV_MASK = 0xffffff, 79 FRACDIV_SHIFT = 0, 80 81 /* PLL CON3 */ 82 WORK_MODE_SHIFT = 8, 83 WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, 84 WORK_MODE_SLOW = 0, 85 WORK_MODE_NORMAL = 1, 86 DSMPD_SHIFT = 3, 87 DSMPD_MASK = 1 << DSMPD_SHIFT, 88 INTEGER_MODE = 1, 89 GLOBAL_POWER_DOWN_SHIFT = 0, 90 GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, 91 GLOBAL_POWER_DOWN = 1, 92 GLOBAL_POWER_UP = 0, 93 94 /* CLKSEL0_CON */ 95 CORE_PLL_SEL_SHIFT = 8, 96 CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, 97 CORE_PLL_SEL_APLL = 0, 98 CORE_PLL_SEL_GPLL = 1, 99 CORE_PLL_SEL_DPLL = 2, 100 CORE_CLK_DIV_SHIFT = 0, 101 CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, 102 103 /* CLKSEL_CON1 */ 104 PCLK_DBG_DIV_CON_SHIFT = 4, 105 PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, 106 ACLK_CORE_DIV_CON_SHIFT = 0, 107 ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, 108 109 /* CLKSEL_CON2 */ 110 ACLK_BUS_PLL_SEL_SHIFT = 8, 111 ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, 112 ACLK_BUS_PLL_SEL_GPLL = 0, 113 ACLK_BUS_PLL_SEL_APLL = 1, 114 ACLK_BUS_PLL_SEL_DPLL = 2, 115 ACLK_BUS_DIV_CON_SHIFT = 0, 116 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 117 ACLK_BUS_DIV_CON_WIDTH = 5, 118 119 /* CLKSEL_CON3 */ 120 PCLK_BUS_DIV_CON_SHIFT = 8, 121 PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, 122 HCLK_BUS_DIV_CON_SHIFT = 0, 123 HCLK_BUS_DIV_CON_MASK = 0x1f, 124 125 /* CLKSEL_CON4 */ 126 CLK_DDR_PLL_SEL_SHIFT = 8, 127 CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, 128 CLK_DDR_DIV_CON_SHIFT = 0, 129 CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, 130 131 /* CLKSEL_CON22 */ 132 CLK_SARADC_DIV_CON_SHIFT = 0, 133 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 134 CLK_SARADC_DIV_CON_WIDTH = 10, 135 136 /* CLKSEL_CON23 */ 137 ACLK_PERI_PLL_SEL_SHIFT = 15, 138 ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, 139 ACLK_PERI_PLL_SEL_GPLL = 0, 140 ACLK_PERI_PLL_SEL_DPLL = 1, 141 PCLK_PERI_DIV_CON_SHIFT = 10, 142 PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, 143 HCLK_PERI_DIV_CON_SHIFT = 5, 144 HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, 145 ACLK_PERI_DIV_CON_SHIFT = 0, 146 ACLK_PERI_DIV_CON_MASK = 0x1f, 147 PERI_DIV_CON_WIDTH = 5, 148 149 /* CLKSEL24_CON */ 150 MAC_PLL_SEL_SHIFT = 12, 151 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 152 MAC_PLL_SEL_APLL = 0, 153 MAC_PLL_SEL_GPLL = 1, 154 RMII_EXTCLK_SEL_SHIFT = 8, 155 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 156 MAC_CLK_DIV_MASK = 0x1f, 157 MAC_CLK_DIV_SHIFT = 0, 158 159 /* CLKSEL27_CON */ 160 SFC_PLL_SEL_SHIFT = 7, 161 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 162 SFC_PLL_SEL_DPLL = 0, 163 SFC_PLL_SEL_GPLL = 1, 164 SFC_CLK_DIV_SHIFT = 0, 165 SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, 166 167 /* CLKSEL28_CON */ 168 ACLK_VIO1_PLL_SEL_SHIFT = 14, 169 ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, 170 VIO_PLL_SEL_DPLL = 0, 171 VIO_PLL_SEL_GPLL = 1, 172 ACLK_VIO1_CLK_DIV_SHIFT = 8, 173 ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, 174 CLK_VIO_DIV_CON_WIDTH = 5, 175 ACLK_VIO0_PLL_SEL_SHIFT = 6, 176 ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, 177 ACLK_VIO0_CLK_DIV_SHIFT = 0, 178 ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, 179 180 /* CLKSEL29_CON */ 181 PCLK_VIO_CLK_DIV_SHIFT = 8, 182 PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, 183 HCLK_VIO_CLK_DIV_SHIFT = 0, 184 HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, 185 186 /* CLKSEL32_CON */ 187 DCLK_VOP_SEL_SHIFT = 7, 188 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 189 DCLK_VOP_SEL_HDMI = 0, 190 DCLK_VOP_SEL_PLL = 1, 191 DCLK_VOP_PLL_SEL_SHIFT = 6, 192 DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, 193 DCLK_VOP_PLL_SEL_GPLL = 0, 194 DCLK_VOP_PLL_SEL_DPLL = 1, 195 DCLK_VOP_CLK_DIV_SHIFT = 0, 196 DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, 197 DCLK_VOP_DIV_CON_WIDTH = 6, 198 199 /* SOFTRST1_CON*/ 200 DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, 201 DDRPHY_SRSTN_CLKDIV_REQ = 1, 202 DDRPHY_SRSTN_CLKDIV_DIS = 0, 203 DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, 204 DDRPHY_SRSTN_REQ_SHIFT = 1, 205 DDRPHY_SRSTN_REQ = 1, 206 DDRPHY_SRSTN_DIS = 0, 207 DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, 208 DDRPHY_PSRSTN_REQ_SHIFT = 2, 209 DDRPHY_PSRSTN_REQ = 1, 210 DDRPHY_PSRSTN_DIS = 0, 211 DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, 212 213 /* SOFTRST2_CON*/ 214 DDRUPCTL_PSRSTN_REQ_SHIFT = 0, 215 DDRUPCTL_PSRSTN_REQ = 1, 216 DDRUPCTL_PSRSTN_DIS = 0, 217 DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, 218 DDRUPCTL_NSRSTN_REQ_SHIFT = 1, 219 DDRUPCTL_NSRSTN_REQ = 1, 220 DDRUPCTL_NSRSTN_DIS = 0, 221 DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, 222 }; 223 #endif 224