1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1108_H 8 #define _ASM_ARCH_CRU_RV1108_H 9 10 #include <common.h> 11 12 #define OSC_HZ (24 * 1000 * 1000) 13 14 #define APLL_HZ (600 * 1000000) 15 #define GPLL_HZ (1188 * 1000000) 16 #define ACLK_PERI_HZ (148500000) 17 #define HCLK_PERI_HZ (148500000) 18 #define PCLK_PERI_HZ (74250000) 19 #define ACLK_BUS_HZ (148500000) 20 21 struct rv1108_clk_priv { 22 struct rv1108_cru *cru; 23 ulong rate; 24 }; 25 26 struct rv1108_cru { 27 struct rv1108_pll { 28 unsigned int con0; 29 unsigned int con1; 30 unsigned int con2; 31 unsigned int con3; 32 unsigned int con4; 33 unsigned int con5; 34 unsigned int reserved[2]; 35 } pll[3]; 36 unsigned int clksel_con[46]; 37 unsigned int reserved1[2]; 38 unsigned int clkgate_con[20]; 39 unsigned int reserved2[4]; 40 unsigned int softrst_con[13]; 41 unsigned int reserved3[3]; 42 unsigned int glb_srst_fst_val; 43 unsigned int glb_srst_snd_val; 44 unsigned int glb_cnt_th; 45 unsigned int misc_con; 46 unsigned int glb_rst_con; 47 unsigned int glb_rst_st; 48 unsigned int sdmmc_con[2]; 49 unsigned int sdio_con[2]; 50 unsigned int emmc_con[2]; 51 }; 52 check_member(rv1108_cru, emmc_con[1], 0x01ec); 53 54 struct pll_div { 55 u32 refdiv; 56 u32 fbdiv; 57 u32 postdiv1; 58 u32 postdiv2; 59 u32 frac; 60 }; 61 62 enum { 63 /* PLL CON0 */ 64 FBDIV_MASK = 0xfff, 65 FBDIV_SHIFT = 0, 66 67 /* PLL CON1 */ 68 POSTDIV2_SHIFT = 12, 69 POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, 70 POSTDIV1_SHIFT = 8, 71 POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, 72 REFDIV_MASK = 0x3f, 73 REFDIV_SHIFT = 0, 74 75 /* PLL CON2 */ 76 LOCK_STA_SHIFT = 31, 77 LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, 78 FRACDIV_MASK = 0xffffff, 79 FRACDIV_SHIFT = 0, 80 81 /* PLL CON3 */ 82 WORK_MODE_SHIFT = 8, 83 WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, 84 WORK_MODE_SLOW = 0, 85 WORK_MODE_NORMAL = 1, 86 DSMPD_SHIFT = 3, 87 DSMPD_MASK = 1 << DSMPD_SHIFT, 88 INTEGER_MODE = 1, 89 GLOBAL_POWER_DOWN_SHIFT = 0, 90 GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, 91 GLOBAL_POWER_DOWN = 1, 92 GLOBAL_POWER_UP = 0, 93 94 /* CLKSEL0_CON */ 95 CORE_PLL_SEL_SHIFT = 8, 96 CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, 97 CORE_PLL_SEL_APLL = 0, 98 CORE_PLL_SEL_GPLL = 1, 99 CORE_PLL_SEL_DPLL = 2, 100 CORE_CLK_DIV_SHIFT = 0, 101 CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, 102 103 /* CLKSEL_CON1 */ 104 PCLK_DBG_DIV_CON_SHIFT = 4, 105 PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, 106 ACLK_CORE_DIV_CON_SHIFT = 0, 107 ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, 108 109 /* CLKSEL_CON2 */ 110 ACLK_BUS_PLL_SEL_SHIFT = 8, 111 ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, 112 ACLK_BUS_PLL_SEL_GPLL = 0, 113 ACLK_BUS_PLL_SEL_APLL = 1, 114 ACLK_BUS_PLL_SEL_DPLL = 2, 115 ACLK_BUS_DIV_CON_SHIFT = 0, 116 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 117 ACLK_BUS_DIV_CON_WIDTH = 5, 118 119 /* CLKSEL_CON3 */ 120 PCLK_BUS_DIV_CON_SHIFT = 8, 121 PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, 122 HCLK_BUS_DIV_CON_SHIFT = 0, 123 HCLK_BUS_DIV_CON_MASK = 0x1f, 124 125 /* CLKSEL_CON4 */ 126 CLK_DDR_PLL_SEL_SHIFT = 8, 127 CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, 128 CLK_DDR_DIV_CON_SHIFT = 0, 129 CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, 130 131 /* CLKSEL_CON19 */ 132 CLK_I2C1_PLL_SEL_SHIFT = 15, 133 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 134 CLK_I2C1_PLL_SEL_DPLL = 0, 135 CLK_I2C1_PLL_SEL_GPLL = 1, 136 CLK_I2C1_DIV_CON_SHIFT = 8, 137 CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, 138 CLK_I2C0_PLL_SEL_SHIFT = 7, 139 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 140 CLK_I2C0_DIV_CON_SHIFT = 0, 141 CLK_I2C0_DIV_CON_MASK = 0x7f, 142 I2C_DIV_CON_WIDTH = 7, 143 144 /* CLKSEL_CON20 */ 145 CLK_I2C3_PLL_SEL_SHIFT = 15, 146 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 147 CLK_I2C3_PLL_SEL_DPLL = 0, 148 CLK_I2C3_PLL_SEL_GPLL = 1, 149 CLK_I2C3_DIV_CON_SHIFT = 8, 150 CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, 151 CLK_I2C2_PLL_SEL_SHIFT = 7, 152 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 153 CLK_I2C2_DIV_CON_SHIFT = 0, 154 CLK_I2C2_DIV_CON_MASK = 0x7f, 155 156 /* CLKSEL_CON22 */ 157 CLK_SARADC_DIV_CON_SHIFT = 0, 158 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 159 CLK_SARADC_DIV_CON_WIDTH = 10, 160 161 /* CLKSEL_CON23 */ 162 ACLK_PERI_PLL_SEL_SHIFT = 15, 163 ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, 164 ACLK_PERI_PLL_SEL_GPLL = 0, 165 ACLK_PERI_PLL_SEL_DPLL = 1, 166 PCLK_PERI_DIV_CON_SHIFT = 10, 167 PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, 168 HCLK_PERI_DIV_CON_SHIFT = 5, 169 HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, 170 ACLK_PERI_DIV_CON_SHIFT = 0, 171 ACLK_PERI_DIV_CON_MASK = 0x1f, 172 PERI_DIV_CON_WIDTH = 5, 173 174 /* CLKSEL24_CON */ 175 MAC_PLL_SEL_SHIFT = 12, 176 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 177 MAC_PLL_SEL_APLL = 0, 178 MAC_PLL_SEL_GPLL = 1, 179 RMII_EXTCLK_SEL_SHIFT = 8, 180 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 181 MAC_CLK_DIV_MASK = 0x1f, 182 MAC_CLK_DIV_SHIFT = 0, 183 184 /* CLKSEL25_CON */ 185 EMMC_PLL_SEL_SHIFT = 12, 186 EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, 187 EMMC_PLL_SEL_DPLL = 0, 188 EMMC_PLL_SEL_GPLL, 189 EMMC_PLL_SEL_OSC, 190 191 /* CLKSEL26_CON */ 192 EMMC_CLK_DIV_SHIFT = 8, 193 EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, 194 195 /* CLKSEL27_CON */ 196 NANDC_PLL_SEL_SHIFT = 14, 197 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 198 NANDC_PLL_SEL_CPLL = 0, 199 NANDC_PLL_SEL_GPLL, 200 NANDC_CLK_DIV_SHIFT = 8, 201 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 202 203 SFC_PLL_SEL_SHIFT = 7, 204 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 205 SFC_PLL_SEL_DPLL = 0, 206 SFC_PLL_SEL_GPLL = 1, 207 SFC_CLK_DIV_SHIFT = 0, 208 SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, 209 210 /* CLKSEL28_CON */ 211 ACLK_VIO1_PLL_SEL_SHIFT = 14, 212 ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, 213 VIO_PLL_SEL_DPLL = 0, 214 VIO_PLL_SEL_GPLL = 1, 215 ACLK_VIO1_CLK_DIV_SHIFT = 8, 216 ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, 217 CLK_VIO_DIV_CON_WIDTH = 5, 218 ACLK_VIO0_PLL_SEL_SHIFT = 6, 219 ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, 220 ACLK_VIO0_CLK_DIV_SHIFT = 0, 221 ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, 222 223 /* CLKSEL29_CON */ 224 PCLK_VIO_CLK_DIV_SHIFT = 8, 225 PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, 226 HCLK_VIO_CLK_DIV_SHIFT = 0, 227 HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, 228 229 /* CLKSEL32_CON */ 230 DCLK_VOP_SEL_SHIFT = 7, 231 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 232 DCLK_VOP_SEL_HDMI = 0, 233 DCLK_VOP_SEL_PLL = 1, 234 DCLK_VOP_PLL_SEL_SHIFT = 6, 235 DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, 236 DCLK_VOP_PLL_SEL_GPLL = 0, 237 DCLK_VOP_PLL_SEL_DPLL = 1, 238 DCLK_VOP_CLK_DIV_SHIFT = 0, 239 DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, 240 DCLK_VOP_DIV_CON_WIDTH = 6, 241 242 /* SOFTRST1_CON*/ 243 DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, 244 DDRPHY_SRSTN_CLKDIV_REQ = 1, 245 DDRPHY_SRSTN_CLKDIV_DIS = 0, 246 DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, 247 DDRPHY_SRSTN_REQ_SHIFT = 1, 248 DDRPHY_SRSTN_REQ = 1, 249 DDRPHY_SRSTN_DIS = 0, 250 DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, 251 DDRPHY_PSRSTN_REQ_SHIFT = 2, 252 DDRPHY_PSRSTN_REQ = 1, 253 DDRPHY_PSRSTN_DIS = 0, 254 DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, 255 256 /* SOFTRST2_CON*/ 257 DDRUPCTL_PSRSTN_REQ_SHIFT = 0, 258 DDRUPCTL_PSRSTN_REQ = 1, 259 DDRUPCTL_PSRSTN_DIS = 0, 260 DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, 261 DDRUPCTL_NSRSTN_REQ_SHIFT = 1, 262 DDRUPCTL_NSRSTN_REQ = 1, 263 DDRUPCTL_NSRSTN_DIS = 0, 264 DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, 265 }; 266 #endif 267