1*bae2f282SAndy Yan /* 2*bae2f282SAndy Yan * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*bae2f282SAndy Yan * Author: Andy Yan <andy.yan@rock-chips.com> 4*bae2f282SAndy Yan * SPDX-License-Identifier: GPL-2.0+ 5*bae2f282SAndy Yan */ 6*bae2f282SAndy Yan #ifndef _ASM_ARCH_CRU_RV1108_H 7*bae2f282SAndy Yan #define _ASM_ARCH_CRU_RV1108_H 8*bae2f282SAndy Yan 9*bae2f282SAndy Yan #include <common.h> 10*bae2f282SAndy Yan 11*bae2f282SAndy Yan #define OSC_HZ (24 * 1000 * 1000) 12*bae2f282SAndy Yan 13*bae2f282SAndy Yan #define APLL_HZ (600 * 1000000) 14*bae2f282SAndy Yan #define GPLL_HZ (594 * 1000000) 15*bae2f282SAndy Yan 16*bae2f282SAndy Yan struct rv1108_clk_priv { 17*bae2f282SAndy Yan struct rv1108_cru *cru; 18*bae2f282SAndy Yan ulong rate; 19*bae2f282SAndy Yan }; 20*bae2f282SAndy Yan 21*bae2f282SAndy Yan struct rv1108_cru { 22*bae2f282SAndy Yan struct rv1108_pll { 23*bae2f282SAndy Yan unsigned int con0; 24*bae2f282SAndy Yan unsigned int con1; 25*bae2f282SAndy Yan unsigned int con2; 26*bae2f282SAndy Yan unsigned int con3; 27*bae2f282SAndy Yan unsigned int con4; 28*bae2f282SAndy Yan unsigned int con5; 29*bae2f282SAndy Yan unsigned int reserved[2]; 30*bae2f282SAndy Yan } pll[3]; 31*bae2f282SAndy Yan unsigned int clksel_con[46]; 32*bae2f282SAndy Yan unsigned int reserved1[2]; 33*bae2f282SAndy Yan unsigned int clkgate_con[20]; 34*bae2f282SAndy Yan unsigned int reserved2[4]; 35*bae2f282SAndy Yan unsigned int softrst_con[13]; 36*bae2f282SAndy Yan unsigned int reserved3[3]; 37*bae2f282SAndy Yan unsigned int glb_srst_fst_val; 38*bae2f282SAndy Yan unsigned int glb_srst_snd_val; 39*bae2f282SAndy Yan unsigned int glb_cnt_th; 40*bae2f282SAndy Yan unsigned int misc_con; 41*bae2f282SAndy Yan unsigned int glb_rst_con; 42*bae2f282SAndy Yan unsigned int glb_rst_st; 43*bae2f282SAndy Yan unsigned int sdmmc_con[2]; 44*bae2f282SAndy Yan unsigned int sdio_con[2]; 45*bae2f282SAndy Yan unsigned int emmc_con[2]; 46*bae2f282SAndy Yan }; 47*bae2f282SAndy Yan check_member(rv1108_cru, emmc_con[1], 0x01ec); 48*bae2f282SAndy Yan 49*bae2f282SAndy Yan struct pll_div { 50*bae2f282SAndy Yan u32 refdiv; 51*bae2f282SAndy Yan u32 fbdiv; 52*bae2f282SAndy Yan u32 postdiv1; 53*bae2f282SAndy Yan u32 postdiv2; 54*bae2f282SAndy Yan u32 frac; 55*bae2f282SAndy Yan }; 56*bae2f282SAndy Yan 57*bae2f282SAndy Yan enum { 58*bae2f282SAndy Yan /* PLL CON0 */ 59*bae2f282SAndy Yan FBDIV_MASK = 0xfff, 60*bae2f282SAndy Yan FBDIV_SHIFT = 0, 61*bae2f282SAndy Yan 62*bae2f282SAndy Yan /* PLL CON1 */ 63*bae2f282SAndy Yan POSTDIV2_SHIFT = 12, 64*bae2f282SAndy Yan POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, 65*bae2f282SAndy Yan POSTDIV1_SHIFT = 8, 66*bae2f282SAndy Yan POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, 67*bae2f282SAndy Yan REFDIV_MASK = 0x3f, 68*bae2f282SAndy Yan REFDIV_SHIFT = 0, 69*bae2f282SAndy Yan 70*bae2f282SAndy Yan /* PLL CON2 */ 71*bae2f282SAndy Yan LOCK_STA_SHIFT = 31, 72*bae2f282SAndy Yan LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, 73*bae2f282SAndy Yan FRACDIV_MASK = 0xffffff, 74*bae2f282SAndy Yan FRACDIV_SHIFT = 0, 75*bae2f282SAndy Yan 76*bae2f282SAndy Yan /* PLL CON3 */ 77*bae2f282SAndy Yan WORK_MODE_SHIFT = 8, 78*bae2f282SAndy Yan WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, 79*bae2f282SAndy Yan WORK_MODE_SLOW = 0, 80*bae2f282SAndy Yan WORK_MODE_NORMAL = 1, 81*bae2f282SAndy Yan DSMPD_SHIFT = 3, 82*bae2f282SAndy Yan DSMPD_MASK = 1 << DSMPD_SHIFT, 83*bae2f282SAndy Yan 84*bae2f282SAndy Yan /* CLKSEL0_CON */ 85*bae2f282SAndy Yan CORE_PLL_SEL_SHIFT = 8, 86*bae2f282SAndy Yan CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, 87*bae2f282SAndy Yan CORE_PLL_SEL_APLL = 0, 88*bae2f282SAndy Yan CORE_PLL_SEL_GPLL = 1, 89*bae2f282SAndy Yan CORE_PLL_SEL_DPLL = 2, 90*bae2f282SAndy Yan CORE_CLK_DIV_SHIFT = 0, 91*bae2f282SAndy Yan CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, 92*bae2f282SAndy Yan 93*bae2f282SAndy Yan /* CLKSEL24_CON */ 94*bae2f282SAndy Yan MAC_PLL_SEL_SHIFT = 12, 95*bae2f282SAndy Yan MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 96*bae2f282SAndy Yan MAC_PLL_SEL_APLL = 0, 97*bae2f282SAndy Yan MAC_PLL_SEL_GPLL = 1, 98*bae2f282SAndy Yan RMII_EXTCLK_SEL_SHIFT = 8, 99*bae2f282SAndy Yan RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 100*bae2f282SAndy Yan MAC_CLK_DIV_MASK = 0x1f, 101*bae2f282SAndy Yan MAC_CLK_DIV_SHIFT = 0, 102*bae2f282SAndy Yan 103*bae2f282SAndy Yan /* CLKSEL27_CON */ 104*bae2f282SAndy Yan SFC_PLL_SEL_SHIFT = 7, 105*bae2f282SAndy Yan SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 106*bae2f282SAndy Yan SFC_PLL_SEL_DPLL = 0, 107*bae2f282SAndy Yan SFC_PLL_SEL_GPLL = 1, 108*bae2f282SAndy Yan SFC_CLK_DIV_SHIFT = 0, 109*bae2f282SAndy Yan SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, 110*bae2f282SAndy Yan }; 111*bae2f282SAndy Yan #endif 112