1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1106_H 8 #define _ASM_ARCH_CRU_RV1106_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #define APLL_HZ (816 * MHz) 17 #define GPLL_HZ (1188 * MHz) 18 #define CPLL_HZ (1000 * MHz) 19 20 /* RV1106 pll id */ 21 enum rv1106_pll_id { 22 APLL, 23 DPLL, 24 CPLL, 25 GPLL, 26 PLL_COUNT, 27 }; 28 29 struct rv1106_clk_info { 30 unsigned long id; 31 char *name; 32 bool is_cru; 33 }; 34 35 struct rv1106_clk_priv { 36 struct rv1106_cru *cru; 37 struct rv1106_grf *grf; 38 ulong gpll_hz; 39 ulong cpll_hz; 40 ulong armclk_hz; 41 ulong armclk_enter_hz; 42 ulong armclk_init_hz; 43 bool sync_kernel; 44 bool set_armclk_rate; 45 }; 46 47 struct rv1106_grf_clk_priv { 48 struct rv1106_grf *grf; 49 }; 50 51 struct rv1106_pll { 52 unsigned int con0; 53 unsigned int con1; 54 unsigned int con2; 55 unsigned int con3; 56 unsigned int con4; 57 unsigned int reserved0[3]; 58 }; 59 60 struct rv1106_cru { 61 unsigned int reserved0[192]; 62 unsigned int pmu_clksel_con[8]; 63 unsigned int reserved1[312]; 64 unsigned int pmu_clkgate_con[3]; 65 unsigned int reserved2[125]; 66 unsigned int pmu_softrst_con[3]; 67 unsigned int reserved3[15741]; 68 struct rv1106_pll pll[4]; 69 unsigned int reserved4[128]; 70 unsigned int mode; 71 unsigned int reserved5[31]; 72 unsigned int clksel_con[34]; 73 unsigned int reserved6[286]; 74 unsigned int clkgate_con[4]; 75 unsigned int reserved7[124]; 76 unsigned int softrst_con[3]; 77 unsigned int reserved8[125]; 78 unsigned int glb_cnt_th; 79 unsigned int glb_rst_st; 80 unsigned int glb_srst_fst; 81 unsigned int glb_srst_snd; 82 unsigned int glb_rst_con; 83 unsigned int con[2]; 84 unsigned int sdmmc_con[2]; 85 unsigned int emmc_con[2]; 86 unsigned int reserved9[1461]; 87 unsigned int peri_clksel_con[12]; 88 unsigned int reserved10[308]; 89 unsigned int peri_clkgate_con[8]; 90 unsigned int reserved11[120]; 91 unsigned int peri_softrst_con[8]; 92 unsigned int reserved12[1592]; 93 unsigned int vi_clksel_con[4]; 94 unsigned int reserved13[316]; 95 unsigned int vi_clkgate_con[3]; 96 unsigned int reserved14[125]; 97 unsigned int vi_softrst_con[3]; 98 unsigned int reserved15[3645]; 99 unsigned int core_clksel_con[5]; 100 unsigned int reserved16[2043]; 101 unsigned int vepu_clksel_con[2]; 102 unsigned int reserved17[318]; 103 unsigned int vepu_clkgate_con[3]; 104 unsigned int reserved18[125]; 105 unsigned int vepu_softrst_con[2]; 106 unsigned int reserved19[1598]; 107 unsigned int vo_clksel_con[4]; 108 unsigned int reserved20[316]; 109 unsigned int vo_clkgate_con[3]; 110 unsigned int reserved21[125]; 111 unsigned int vo_softrst_con[4]; 112 }; 113 check_member(rv1106_cru, vo_softrst_con[0], 0x1ca00); 114 115 struct pll_rate_table { 116 unsigned long rate; 117 unsigned int fbdiv; 118 unsigned int postdiv1; 119 unsigned int refdiv; 120 unsigned int postdiv2; 121 unsigned int dsmpd; 122 unsigned int frac; 123 }; 124 125 #define RV1106_TOPCRU_BASE 0x10000 126 #define RV1106_SUBDDRCRU_BASE 0x1F000 127 128 #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE) 129 #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE) 130 #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE) 131 132 enum { 133 /* CRU_PMU_CLK_SEL0_CON */ 134 CLK_I2C1_SEL_SHIFT = 6, 135 CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 136 CLK_I2C1_SEL_200M = 0, 137 CLK_I2C1_SEL_100M, 138 CLK_I2C1_SEL_24M, 139 CLK_I2C1_SEL_32K, 140 HCLK_PMU_SEL_SHIFT = 4, 141 HCLK_PMU_SEL_MASK = 0x3 << HCLK_PMU_SEL_SHIFT, 142 HCLK_PMU_SEL_200M = 0, 143 HCLK_PMU_SEL_100M, 144 HCLK_PMU_SEL_24M, 145 PCLK_PMU_SEL_SHIFT = 3, 146 PCLK_PMU_SEL_MASK = 0x1 << PCLK_PMU_SEL_SHIFT, 147 PCLK_PMU_SEL_100M = 0, 148 PCLK_PMU_SEL_24M, 149 150 /* CRU_CLK_SEL5_CON */ 151 CLK_UART_SRC_SEL_SHIFT = 5, 152 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 153 CLK_UART_SRC_SEL_GPLL = 0, 154 CLK_UART_SRC_SEL_CPLL, 155 CLK_UART_SRC_DIV_SHIFT = 0, 156 CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT, 157 158 /* CRU_CLK_SEL6_CON */ 159 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 160 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 161 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 162 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 163 164 /* CRU_CLK_SEL7_CON */ 165 CLK_UART_SEL_SHIFT = 0, 166 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 167 CLK_UART_SEL_SRC = 0, 168 CLK_UART_SEL_FRAC, 169 CLK_UART_SEL_XIN24M, 170 171 /* CRU_CLK_SEL23_CON */ 172 DCLK_VOP_SEL_SHIFT = 8, 173 DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, 174 DCLK_VOP_SEL_GPLL = 0, 175 DCLK_VOP_SEL_CPLL, 176 DCLK_VOP_DIV_SHIFT = 3, 177 DCLK_VOP_DIV_MASK = 0x1f << DCLK_VOP_DIV_SHIFT, 178 179 /* CRU_CLK_SEL24_CON */ 180 PCLK_TOP_SEL_SHIFT = 5, 181 PCLK_TOP_SEL_MASK = 0x3 << PCLK_TOP_SEL_SHIFT, 182 PCLK_TOP_SEL_100M = 0, 183 PCLK_TOP_SEL_50M, 184 PCLK_TOP_SEL_24M, 185 186 /* CRU_PERI_CLK_SEL1_CON */ 187 CLK_I2C3_SEL_SHIFT = 14, 188 CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, 189 CLK_I2C2_SEL_SHIFT = 12, 190 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 191 CLK_I2C0_SEL_SHIFT = 8, 192 CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 193 CLK_I2C0_SEL_200M = 0, 194 CLK_I2C0_SEL_100M, 195 CLK_I2C0_SEL_50M, 196 CLK_I2C0_SEL_24M, 197 HCLK_PERI_SEL_SHIFT = 4, 198 HCLK_PERI_SEL_MASK = 0x3 << HCLK_PERI_SEL_SHIFT, 199 HCLK_PERI_SEL_200M = 0, 200 HCLK_PERI_SEL_100M, 201 HCLK_PERI_SEL_50M, 202 HCLK_PERI_SEL_24M, 203 ACLK_PERI_SEL_SHIFT = 2, 204 ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT, 205 ACLK_PERI_SEL_400M = 0, 206 ACLK_PERI_SEL_200M, 207 ACLK_PERI_SEL_100M, 208 ACLK_PERI_SEL_24M, 209 PCLK_PERI_SEL_SHIFT = 0, 210 PCLK_PERI_SEL_MASK = 0x3 << PCLK_PERI_SEL_SHIFT, 211 PCLK_PERI_SEL_100M = 0, 212 PCLK_PERI_SEL_50M, 213 PCLK_PERI_SEL_24M, 214 215 /* CRU_PERI_CLK_SEL2_CON */ 216 CLK_I2C4_SEL_SHIFT = 0, 217 CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, 218 219 /* CRU_PERI_CLK_SEL6_CON */ 220 CLK_PWM2_SEL_SHIFT = 11, 221 CLK_PWM2_SEL_MASK = 0x3 << CLK_PWM2_SEL_SHIFT, 222 CLK_PWM1_SEL_SHIFT = 9, 223 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 224 CLK_PWM_SEL_100M = 0, 225 CLK_PWM_SEL_50M, 226 CLK_PWM_SEL_24M, 227 CLK_PKA_CRYPTO_SEL_SHIFT = 7, 228 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 229 CLK_CORE_CRYPTO_SEL_SHIFT = 5, 230 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 231 CLK_CRYPTO_SEL_300M = 0, 232 CLK_CRYPTO_SEL_200M, 233 CLK_CRYPTO_SEL_100M, 234 CLK_CRYPTO_SEL_24M, 235 CLK_SARADC_DIV_SHIFT = 0, 236 CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 237 CLK_SPI1_SEL_SHIFT = 3, 238 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 239 240 /* CRU_PERI_CLK_SEL7_CON */ 241 DCLK_DECOM_SEL_SHIFT = 14, 242 DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT, 243 DCLK_DECOM_SEL_400M = 0, 244 DCLK_DECOM_SEL_200M, 245 DCLK_DECOM_SEL_100M, 246 DCLK_DECOM_SEL_24M, 247 CLK_SFC_SEL_SHIFT = 12, 248 CLK_SFC_SEL_MASK = 0x3 << CLK_SFC_SEL_SHIFT, 249 CLK_SFC_SEL_500M = 0, 250 CLK_SFC_SEL_300M, 251 CLK_SFC_SEL_200M, 252 CLK_SFC_SEL_24M, 253 CLK_SFC_DIV_SHIFT = 7, 254 CLK_SFC_DIV_MASK = 0x1f << CLK_SFC_DIV_SHIFT, 255 CLK_EMMC_SEL_SHIFT = 6, 256 CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT, 257 CLK_MMC_SEL_400M = 0, 258 CLK_MMC_SEL_24M, 259 CLK_EMMC_DIV_SHIFT = 0, 260 CLK_EMMC_DIV_MASK = 0x3f << CLK_EMMC_DIV_SHIFT, 261 262 /* CRU_PERI_CLK_SEL9_CON */ 263 ACLK_BUS_SEL_SHIFT = 0, 264 ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 265 ACLK_BUS_SEL_300M = 0, 266 ACLK_BUS_SEL_200M, 267 ACLK_BUS_SEL_100M, 268 ACLK_BUS_SEL_24M, 269 270 /* CRU_PERI_CLK_SEL11_CON */ 271 CLK_PWM0_SEL_SHIFT = 0, 272 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, 273 274 /* CRU_VEPU_CLK_SEL0_CON */ 275 CLK_SPI0_SEL_SHIFT = 12, 276 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 277 CLK_SPI0_SEL_200M = 0, 278 CLK_SPI0_SEL_100M, 279 CLK_SPI0_SEL_50M, 280 CLK_SPI0_SEL_24M, 281 282 /* CRU_CORE_CLK_SEL0_CON */ 283 CLK_CORE_DIV_SHIFT = 0, 284 CLK_CORE_DIV_MASK = 0x1f << CLK_CORE_DIV_SHIFT, 285 286 /* CRU_VI_CLK_SEL1_CON */ 287 CLK_SDMMC_SEL_SHIFT = 14, 288 CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT, 289 CLK_SDMMC_DIV_SHIFT = 8, 290 CLK_SDMMC_DIV_MASK = 0x3f << CLK_SDMMC_DIV_SHIFT, 291 292 /* CRU_VO_CLK_SEL1_CON */ 293 ACLK_VOP_SEL_SHIFT = 10, 294 ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT, 295 ACLK_VOP_SEL_300M = 0, 296 ACLK_VOP_SEL_200M, 297 ACLK_VOP_SEL_100M, 298 ACLK_VOP_SEL_24M, 299 300 /* CRU_VO_CLK_SEL3_CON */ 301 CLK_TSADC_TSEN_DIV_SHIFT = 5, 302 CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, 303 CLK_TSADC_DIV_SHIFT = 0, 304 CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, 305 }; 306 #endif 307