1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3588_H 8 #define _ASM_ARCH_CRU_RK3588_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define LPLL_HZ (1200 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (1500 * MHz) 17 #define NPLL_HZ (850 * MHz) 18 #define PPLL_HZ (100 * MHz) 19 20 /* RK3588 pll id */ 21 enum rk3588_pll_id { 22 B0PLL, 23 B1PLL, 24 LPLL, 25 CPLL, 26 GPLL, 27 NPLL, 28 V0PLL, 29 AUPLL, 30 PPLL, 31 PLL_COUNT, 32 }; 33 34 struct rk3588_clk_info { 35 unsigned long id; 36 char *name; 37 bool is_cru; 38 }; 39 40 struct rk3588_clk_priv { 41 struct rk3588_cru *cru; 42 struct rk3588_grf *grf; 43 ulong ppll_hz; 44 ulong gpll_hz; 45 ulong cpll_hz; 46 ulong npll_hz; 47 ulong v0pll_hz; 48 ulong aupll_hz; 49 ulong armclk_hz; 50 ulong armclk_enter_hz; 51 ulong armclk_init_hz; 52 bool sync_kernel; 53 bool set_armclk_rate; 54 }; 55 56 struct rk3588_pll { 57 unsigned int con0; 58 unsigned int con1; 59 unsigned int con2; 60 unsigned int con3; 61 unsigned int con4; 62 unsigned int reserved0[3]; 63 }; 64 65 struct rk3588_cru { 66 struct rk3588_pll pll[18]; 67 unsigned int reserved0[16];/* Address Offset: 0x0240 */ 68 unsigned int mode_con00;/* Address Offset: 0x0280 */ 69 unsigned int reserved1[31];/* Address Offset: 0x0284 */ 70 unsigned int clksel_con[178]; /* Address Offset: 0x0300 */ 71 unsigned int reserved2[142];/* Address Offset: 0x05c8 */ 72 unsigned int clkgate_con[78];/* Address Offset: 0x0800 */ 73 unsigned int reserved3[50];/* Address Offset: 0x0938 */ 74 unsigned int softrst_con[78];/* Address Offset: 0x0400 */ 75 unsigned int reserved4[50];/* Address Offset: 0x0b38 */ 76 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ 77 unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ 78 unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ 79 unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ 80 unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ 81 unsigned int reserved5[4];/* Address Offset: 0x0c14 */ 82 unsigned int sdio_con[2];/* Address Offset: 0x0c24 */ 83 unsigned int reserved7;/* Address Offset: 0x0c2c */ 84 unsigned int sdmmc_con[2];/* Address Offset: 0x0c30 */ 85 unsigned int reserved8[48562];/* Address Offset: 0x0c38 */ 86 unsigned int pmuclksel_con[21]; /* Address Offset: 0x0100 */ 87 unsigned int reserved9[299];/* Address Offset: 0x0c38 */ 88 unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */ 89 }; 90 91 check_member(rk3588_cru, mode_con00, 0x280); 92 check_member(rk3588_cru, pmuclksel_con[1], 0x30304); 93 94 struct pll_rate_table { 95 unsigned long rate; 96 unsigned int m; 97 unsigned int p; 98 unsigned int s; 99 unsigned int k; 100 }; 101 102 #define RK3588_PLL_CON(x) ((x) * 0x4) 103 #define RK3588_MODE_CON 0x280 104 105 #define RK3588_PHP_CRU_BASE 0x8000 106 #define RK3588_PMU_CRU_BASE 0x30000 107 #define RK3588_BIGCORE0_CRU_BASE 0x50000 108 #define RK3588_BIGCORE1_CRU_BASE 0x52000 109 #define RK3588_DSU_CRU_BASE 0x58000 110 111 #define RK3588_PLL_CON(x) ((x) * 0x4) 112 #define RK3588_MODE_CON0 0x280 113 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 114 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 115 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 116 #define RK3588_GLB_CNT_TH 0xc00 117 #define RK3588_GLB_SRST_FST 0xc08 118 #define RK3588_GLB_SRST_SND 0xc0c 119 #define RK3588_GLB_RST_CON 0xc10 120 #define RK3588_GLB_RST_ST 0xc04 121 #define RK3588_SDIO_CON0 0xC24 122 #define RK3588_SDIO_CON1 0xC28 123 #define RK3588_SDMMC_CON0 0xC30 124 #define RK3588_SDMMC_CON1 0xC34 125 126 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) 127 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) 128 129 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) 130 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) 131 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) 132 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) 133 134 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) 135 #define RK3588_B0_PLL_MODE_CON (RK3588_BIGCORE0_CRU_BASE + 0x280) 136 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) 137 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) 138 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) 139 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) 140 #define RK3588_B1_PLL_MODE_CON (RK3588_BIGCORE1_CRU_BASE + 0x280) 141 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) 142 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) 143 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) 144 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) 145 #define RK3588_LPLL_MODE_CON (RK3588_DSU_CRU_BASE + 0x280) 146 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) 147 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) 148 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) 149 150 enum { 151 /* CRU_CLK_SEL8_CON */ 152 ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14, 153 ACLK_LOW_TOP_ROOT_SRC_SEL_MASK = 1 << ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT, 154 ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL = 0, 155 ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL, 156 ACLK_LOW_TOP_ROOT_DIV_SHIFT = 9, 157 ACLK_LOW_TOP_ROOT_DIV_MASK = 0x1f << ACLK_LOW_TOP_ROOT_DIV_SHIFT, 158 PCLK_TOP_ROOT_SEL_SHIFT = 7, 159 PCLK_TOP_ROOT_SEL_MASK = 3 << PCLK_TOP_ROOT_SEL_SHIFT, 160 PCLK_TOP_ROOT_SEL_100M = 0, 161 PCLK_TOP_ROOT_SEL_50M, 162 PCLK_TOP_ROOT_SEL_24M, 163 ACLK_TOP_ROOT_SRC_SEL_SHIFT = 5, 164 ACLK_TOP_ROOT_SRC_SEL_MASK = 3 << ACLK_TOP_ROOT_SRC_SEL_SHIFT, 165 ACLK_TOP_ROOT_SRC_SEL_GPLL = 0, 166 ACLK_TOP_ROOT_SRC_SEL_CPLL, 167 ACLK_TOP_ROOT_SRC_SEL_AUPLL, 168 ACLK_TOP_ROOT_DIV_SHIFT = 0, 169 ACLK_TOP_ROOT_DIV_MASK = 0x1f << ACLK_TOP_ROOT_DIV_SHIFT, 170 171 /* CRU_CLK_SEL9_CON */ 172 ACLK_TOP_S400_SEL_SHIFT = 8, 173 ACLK_TOP_S400_SEL_MASK = 3 << ACLK_TOP_S400_SEL_SHIFT, 174 ACLK_TOP_S400_SEL_400M = 0, 175 ACLK_TOP_S400_SEL_200M, 176 ACLK_TOP_S200_SEL_SHIFT = 6, 177 ACLK_TOP_S200_SEL_MASK = 3 << ACLK_TOP_S200_SEL_SHIFT, 178 ACLK_TOP_S200_SEL_200M = 0, 179 ACLK_TOP_S200_SEL_100M, 180 181 /* CRU_CLK_SEL38_CON */ 182 CLK_I2C8_SEL_SHIFT = 13, 183 CLK_I2C8_SEL_MASK = 1 << CLK_I2C8_SEL_SHIFT, 184 CLK_I2C7_SEL_SHIFT = 12, 185 CLK_I2C7_SEL_MASK = 1 << CLK_I2C7_SEL_SHIFT, 186 CLK_I2C6_SEL_SHIFT = 11, 187 CLK_I2C6_SEL_MASK = 1 << CLK_I2C6_SEL_SHIFT, 188 CLK_I2C5_SEL_SHIFT = 10, 189 CLK_I2C5_SEL_MASK = 1 << CLK_I2C5_SEL_SHIFT, 190 CLK_I2C4_SEL_SHIFT = 9, 191 CLK_I2C4_SEL_MASK = 1 << CLK_I2C4_SEL_SHIFT, 192 CLK_I2C3_SEL_SHIFT = 8, 193 CLK_I2C3_SEL_MASK = 1 << CLK_I2C3_SEL_SHIFT, 194 CLK_I2C2_SEL_SHIFT = 7, 195 CLK_I2C2_SEL_MASK = 1 << CLK_I2C2_SEL_SHIFT, 196 CLK_I2C1_SEL_SHIFT = 6, 197 CLK_I2C1_SEL_MASK = 1 << CLK_I2C1_SEL_SHIFT, 198 ACLK_BUS_ROOT_SEL_SHIFT = 5, 199 ACLK_BUS_ROOT_SEL_MASK = 3 << ACLK_BUS_ROOT_SEL_SHIFT, 200 ACLK_BUS_ROOT_SEL_GPLL = 0, 201 ACLK_BUS_ROOT_SEL_CPLL, 202 ACLK_BUS_ROOT_DIV_SHIFT = 0, 203 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, 204 205 /* CRU_CLK_SEL40_CON */ 206 CLK_SARADC_SEL_SHIFT = 14, 207 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, 208 CLK_SARADC_SEL_GPLL = 0, 209 CLK_SARADC_SEL_24M, 210 CLK_SARADC_DIV_SHIFT = 6, 211 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, 212 213 /* CRU_CLK_SEL41_CON */ 214 CLK_UART_SRC_SEL_SHIFT = 14, 215 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 216 CLK_UART_SRC_SEL_GPLL = 0, 217 CLK_UART_SRC_SEL_CPLL, 218 CLK_UART_SRC_DIV_SHIFT = 9, 219 CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT, 220 CLK_TSADC_SEL_SHIFT = 8, 221 CLK_TSADC_SEL_MASK = 0x1 << CLK_TSADC_SEL_SHIFT, 222 CLK_TSADC_SEL_GPLL = 0, 223 CLK_TSADC_SEL_24M, 224 CLK_TSADC_DIV_SHIFT = 0, 225 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, 226 227 /* CRU_CLK_SEL42_CON */ 228 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 229 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 230 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 231 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 232 233 /* CRU_CLK_SEL43_CON */ 234 CLK_UART_SEL_SHIFT = 0, 235 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 236 CLK_UART_SEL_SRC = 0, 237 CLK_UART_SEL_FRAC, 238 CLK_UART_SEL_XIN24M, 239 240 /* CRU_CLK_SEL59_CON */ 241 CLK_PWM2_SEL_SHIFT = 14, 242 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 243 CLK_PWM1_SEL_SHIFT = 12, 244 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 245 CLK_SPI4_SEL_SHIFT = 10, 246 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, 247 CLK_SPI3_SEL_SHIFT = 8, 248 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 249 CLK_SPI2_SEL_SHIFT = 6, 250 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 251 CLK_SPI1_SEL_SHIFT = 4, 252 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 253 CLK_SPI0_SEL_SHIFT = 2, 254 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 255 CLK_SPI_SEL_200M = 0, 256 CLK_SPI_SEL_150M, 257 CLK_SPI_SEL_24M, 258 259 /* CRU_CLK_SEL60_CON */ 260 CLK_PWM3_SEL_SHIFT = 0, 261 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, 262 CLK_PWM_SEL_100M = 0, 263 CLK_PWM_SEL_50M, 264 CLK_PWM_SEL_24M, 265 266 /* CRU_CLK_SEL62_CON */ 267 DCLK_DECOM_SEL_SHIFT = 5, 268 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 269 DCLK_DECOM_SEL_GPLL = 0, 270 DCLK_DECOM_SEL_SPLL, 271 DCLK_DECOM_DIV_SHIFT = 0, 272 DCLK_DECOM_DIV_MASK = 0x1F << DCLK_DECOM_DIV_SHIFT, 273 274 /* CRU_CLK_SEL77_CON */ 275 CCLK_EMMC_SEL_SHIFT = 14, 276 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, 277 CCLK_EMMC_SEL_GPLL = 0, 278 CCLK_EMMC_SEL_CPLL, 279 CCLK_EMMC_SEL_24M, 280 CCLK_EMMC_DIV_SHIFT = 8, 281 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, 282 283 /* CRU_CLK_SEL78_CON */ 284 SCLK_SFC_SEL_SHIFT = 12, 285 SCLK_SFC_SEL_MASK = 3 << SCLK_SFC_SEL_SHIFT, 286 SCLK_SFC_SEL_GPLL = 0, 287 SCLK_SFC_SEL_CPLL, 288 SCLK_SFC_SEL_24M, 289 SCLK_SFC_DIV_SHIFT = 6, 290 SCLK_SFC_DIV_MASK = 0x3f << SCLK_SFC_DIV_SHIFT, 291 BCLK_EMMC_SEL_SHIFT = 5, 292 BCLK_EMMC_SEL_MASK = 1 << BCLK_EMMC_SEL_SHIFT, 293 BCLK_EMMC_SEL_GPLL = 0, 294 BCLK_EMMC_SEL_CPLL, 295 BCLK_EMMC_DIV_SHIFT = 0, 296 BCLK_EMMC_DIV_MASK = 0x1f << BCLK_EMMC_DIV_SHIFT, 297 298 /* CRU_CLK_SEL81_CON */ 299 CLK_GMAC1_PTP_SEL_SHIFT = 13, 300 CLK_GMAC1_PTP_SEL_MASK = 1 << CLK_GMAC1_PTP_SEL_SHIFT, 301 CLK_GMAC1_PTP_SEL_CPLL = 0, 302 CLK_GMAC1_PTP_DIV_SHIFT = 7, 303 CLK_GMAC1_PTP_DIV_MASK = 0x3f << CLK_GMAC1_PTP_DIV_SHIFT, 304 CLK_GMAC0_PTP_SEL_SHIFT = 6, 305 CLK_GMAC0_PTP_SEL_MASK = 1 << CLK_GMAC0_PTP_SEL_SHIFT, 306 CLK_GMAC0_PTP_SEL_CPLL = 0, 307 CLK_GMAC0_PTP_DIV_SHIFT = 0, 308 CLK_GMAC0_PTP_DIV_MASK = 0x3f << CLK_GMAC0_PTP_DIV_SHIFT, 309 310 /* CRU_CLK_SEL83_CON */ 311 CLK_GMAC_125M_SEL_SHIFT = 15, 312 CLK_GMAC_125M_SEL_MASK = 1 << CLK_GMAC_125M_SEL_SHIFT, 313 CLK_GMAC_125M_SEL_GPLL = 0, 314 CLK_GMAC_125M_SEL_CPLL, 315 CLK_GMAC_125M_DIV_SHIFT = 8, 316 CLK_GMAC_125M_DIV_MASK = 0x7f << CLK_GMAC_125M_DIV_SHIFT, 317 318 /* CRU_CLK_SEL84_CON */ 319 CLK_GMAC_50M_SEL_SHIFT = 7, 320 CLK_GMAC_50M_SEL_MASK = 1 << CLK_GMAC_50M_SEL_SHIFT, 321 CLK_GMAC_50M_SEL_GPLL = 0, 322 CLK_GMAC_50M_SEL_CPLL, 323 CLK_GMAC_50M_DIV_SHIFT = 0, 324 CLK_GMAC_50M_DIV_MASK = 0x7f << CLK_GMAC_50M_DIV_SHIFT, 325 326 /* CRU_CLK_SEL110_CON */ 327 HCLK_VOP_ROOT_SEL_SHIFT = 10, 328 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, 329 HCLK_VOP_ROOT_SEL_200M = 0, 330 HCLK_VOP_ROOT_SEL_100M, 331 HCLK_VOP_ROOT_SEL_50M, 332 HCLK_VOP_ROOT_SEL_24M, 333 ACLK_VOP_LOW_ROOT_SEL_SHIFT = 8, 334 ACLK_VOP_LOW_ROOT_SEL_MASK = 3 << ACLK_VOP_LOW_ROOT_SEL_SHIFT, 335 ACLK_VOP_LOW_ROOT_SEL_400M = 0, 336 ACLK_VOP_LOW_ROOT_SEL_200M, 337 ACLK_VOP_LOW_ROOT_SEL_100M, 338 ACLK_VOP_LOW_ROOT_SEL_24M, 339 ACLK_VOP_ROOT_SEL_SHIFT = 5, 340 ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT, 341 ACLK_VOP_ROOT_SEL_GPLL = 0, 342 ACLK_VOP_ROOT_SEL_CPLL, 343 ACLK_VOP_ROOT_SEL_AUPLL, 344 ACLK_VOP_ROOT_SEL_NPLL, 345 ACLK_VOP_ROOT_SEL_SPLL, 346 ACLK_VOP_ROOT_DIV_SHIFT = 0, 347 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, 348 349 /* CRU_CLK_SEL111_CON */ 350 DCLK1_VOP_SRC_SEL_SHIFT = 14, 351 DCLK1_VOP_SRC_SEL_MASK = 3 << DCLK1_VOP_SRC_SEL_SHIFT, 352 DCLK1_VOP_SRC_DIV_SHIFT = 9, 353 DCLK1_VOP_SRC_DIV_MASK = 0x1f << DCLK1_VOP_SRC_DIV_SHIFT, 354 DCLK0_VOP_SRC_SEL_SHIFT = 7, 355 DCLK0_VOP_SRC_SEL_MASK = 3 << DCLK0_VOP_SRC_SEL_SHIFT, 356 DCLK_VOP_SRC_SEL_GPLL = 0, 357 DCLK_VOP_SRC_SEL_CPLL, 358 DCLK_VOP_SRC_SEL_V0PLL, 359 DCLK_VOP_SRC_SEL_AUPLL, 360 DCLK0_VOP_SRC_DIV_SHIFT = 0, 361 DCLK0_VOP_SRC_DIV_MASK = 0x7f << DCLK0_VOP_SRC_DIV_SHIFT, 362 363 /* CRU_CLK_SEL112_CON */ 364 DCLK2_VOP_SRC_SEL_SHIFT = 5, 365 DCLK2_VOP_SRC_SEL_MASK = 3 << DCLK2_VOP_SRC_SEL_SHIFT, 366 DCLK2_VOP_SRC_DIV_SHIFT = 0, 367 DCLK2_VOP_SRC_DIV_MASK = 0x1f << DCLK2_VOP_SRC_DIV_SHIFT, 368 369 /* CRU_CLK_SEL113_CON */ 370 DCLK3_VOP_SRC_SEL_SHIFT = 7, 371 DCLK3_VOP_SRC_SEL_MASK = 3 << DCLK3_VOP_SRC_SEL_SHIFT, 372 DCLK3_VOP_SRC_DIV_SHIFT = 0, 373 DCLK3_VOP_SRC_DIV_MASK = 0x7f << DCLK3_VOP_SRC_DIV_SHIFT, 374 375 /* CRU_CLK_SEL165_CON */ 376 PCLK_CENTER_ROOT_SEL_SHIFT = 6, 377 PCLK_CENTER_ROOT_SEL_MASK = 3 << PCLK_CENTER_ROOT_SEL_SHIFT, 378 PCLK_CENTER_ROOT_SEL_200M = 0, 379 PCLK_CENTER_ROOT_SEL_100M, 380 PCLK_CENTER_ROOT_SEL_50M, 381 PCLK_CENTER_ROOT_SEL_24M, 382 HCLK_CENTER_ROOT_SEL_SHIFT = 4, 383 HCLK_CENTER_ROOT_SEL_MASK = 3 << HCLK_CENTER_ROOT_SEL_SHIFT, 384 HCLK_CENTER_ROOT_SEL_400M = 0, 385 HCLK_CENTER_ROOT_SEL_200M, 386 HCLK_CENTER_ROOT_SEL_100M, 387 HCLK_CENTER_ROOT_SEL_24M, 388 ACLK_CENTER_LOW_ROOT_SEL_SHIFT = 2, 389 ACLK_CENTER_LOW_ROOT_SEL_MASK = 3 << ACLK_CENTER_LOW_ROOT_SEL_SHIFT, 390 ACLK_CENTER_LOW_ROOT_SEL_500M = 0, 391 ACLK_CENTER_LOW_ROOT_SEL_250M, 392 ACLK_CENTER_LOW_ROOT_SEL_100M, 393 ACLK_CENTER_LOW_ROOT_SEL_24M, 394 ACLK_CENTER_ROOT_SEL_SHIFT = 0, 395 ACLK_CENTER_ROOT_SEL_MASK = 3 << ACLK_CENTER_ROOT_SEL_SHIFT, 396 ACLK_CENTER_ROOT_SEL_700M = 0, 397 ACLK_CENTER_ROOT_SEL_400M, 398 ACLK_CENTER_ROOT_SEL_200M, 399 ACLK_CENTER_ROOT_SEL_24M, 400 401 /* CRU_CLK_SEL172_CON */ 402 CCLK_SDIO_SRC_SEL_SHIFT = 8, 403 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, 404 CCLK_SDIO_SRC_SEL_GPLL = 0, 405 CCLK_SDIO_SRC_SEL_CPLL, 406 CCLK_SDIO_SRC_SEL_24M, 407 CCLK_SDIO_SRC_DIV_SHIFT = 2, 408 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, 409 410 /* CRU_CLK_SEL176_CON */ 411 CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6, 412 CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT, 413 CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0, 414 CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT, 415 416 /* CRU_CLK_SEL177_CON */ 417 CLK_PCIE_PHY2_REF_SEL_SHIFT = 8, 418 CLK_PCIE_PHY2_REF_SEL_MASK = 1 << CLK_PCIE_PHY2_REF_SEL_SHIFT, 419 CLK_PCIE_PHY1_REF_SEL_SHIFT = 7, 420 CLK_PCIE_PHY1_REF_SEL_MASK = 1 << CLK_PCIE_PHY1_REF_SEL_SHIFT, 421 CLK_PCIE_PHY0_REF_SEL_SHIFT = 6, 422 CLK_PCIE_PHY0_REF_SEL_MASK = 1 << CLK_PCIE_PHY0_REF_SEL_SHIFT, 423 CLK_PCIE_PHY_REF_SEL_24M = 0, 424 CLK_PCIE_PHY_REF_SEL_PPLL, 425 CLK_PCIE_PHY2_PLL_DIV_SHIFT = 0, 426 CLK_PCIE_PHY2_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY2_PLL_DIV_SHIFT, 427 428 /* PMUCRU_CLK_SEL3_CON */ 429 CLK_I2C0_SEL_SHIFT = 6, 430 CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT, 431 CLK_I2C_SEL_200M = 0, 432 CLK_I2C_SEL_100M, 433 }; 434 #endif 435