1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3576_H 8 #define _ASM_ARCH_CRU_RK3576_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define CPU_PVTPLL_HZ (1008 * MHz) 15 #define LPLL_HZ (816 * MHz) 16 #define GPLL_HZ (1188 * MHz) 17 #define CPLL_HZ (1000 * MHz) 18 #define PPLL_HZ (1100 * MHz) 19 #define GMAC0_PTP_REFCLK_IN (24 * MHz) 20 #define GMAC1_PTP_REFCLK_IN (24 * MHz) 21 /* RK3576 pll id */ 22 enum rk3576_pll_id { 23 BPLL, 24 LPLL, 25 DPLL, 26 CPLL, 27 GPLL, 28 VPLL, 29 AUPLL, 30 SPLL, 31 PPLL, 32 PLL_COUNT, 33 }; 34 35 struct rk3576_clk_info { 36 unsigned long id; 37 char *name; 38 bool is_cru; 39 }; 40 41 struct rk3576_clk_priv { 42 struct rk3576_cru *cru; 43 struct rk3576_grf *grf; 44 ulong ppll_hz; 45 ulong gpll_hz; 46 ulong cpll_hz; 47 ulong vpll_hz; 48 ulong aupll_hz; 49 ulong spll_hz; 50 ulong lpll_hz; 51 ulong bpll_hz; 52 ulong armclk_hz; 53 ulong armclk_enter_hz; 54 ulong armclk_init_hz; 55 bool sync_kernel; 56 bool set_armclk_rate; 57 }; 58 59 struct rk3576_pll { 60 unsigned int con0; 61 unsigned int con1; 62 unsigned int con2; 63 unsigned int con3; 64 unsigned int con4; 65 unsigned int reserved0[3]; 66 }; 67 68 struct rk3576_cru { 69 struct rk3576_pll pll[18]; 70 unsigned int reserved0[16];/* Address Offset: 0x0240 */ 71 unsigned int mode_con00;/* Address Offset: 0x0280 */ 72 unsigned int reserved1[31];/* Address Offset: 0x0284 */ 73 unsigned int clksel_con[181]; /* Address Offset: 0x0300 */ 74 unsigned int reserved2[139];/* Address Offset: 0x05d4 */ 75 unsigned int clkgate_con[80];/* Address Offset: 0x0800 */ 76 unsigned int reserved3[48];/* Address Offset: 0x0938 */ 77 unsigned int softrst_con[80];/* Address Offset: 0x0400 */ 78 unsigned int reserved4[48];/* Address Offset: 0x0b38 */ 79 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ 80 unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ 81 unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ 82 unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ 83 unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ 84 unsigned int reserved5[43];/* Address Offset: 0x0c14 */ 85 unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */ 86 unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */ 87 unsigned int reserved8[32137];/* Address Offset: 0x0c38 */ 88 unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */ 89 unsigned int reserved9[298];/* Address Offset: 0x20358 */ 90 unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */ 91 unsigned int reserved10[32440];/* Address Offset: 0x20820 */ 92 unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */ 93 }; 94 95 check_member(rk3576_cru, mode_con00, 0x280); 96 check_member(rk3576_cru, pmuclksel_con[1], 0x20304); 97 98 struct pll_rate_table { 99 unsigned long rate; 100 unsigned int m; 101 unsigned int p; 102 unsigned int s; 103 unsigned int k; 104 }; 105 106 #define RK3576_PHP_CRU_BASE 0x8000 107 #define RK3576_PMU_CRU_BASE 0x20000 108 #define RK3576_BIGCORE_CRU_BASE 0x38000 109 #define RK3576_LITCORE_CRU_BASE 0x40000 110 #define RK3576_CCI_CRU_BASE 0x48000 111 #define RK3576_CRU_BASE 0x27200000 112 #define RK3576_SCRU_BASE 0x27214000 113 114 #define RK3576_BIGCORE_GRF_BASE 0x2600C000 115 #define RK3576_LITCORE_GRF_BASE 0x2600E000 116 #define RK3576_CCI_GRF_BASE 0x26010000 117 118 #define RK3576_PLL_CON(x) ((x) * 0x4) 119 #define RK3576_MODE_CON0 0x280 120 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) 121 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) 122 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) 123 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 124 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 125 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 126 #define RK3576_GLB_CNT_TH 0xc00 127 #define RK3576_GLB_SRST_FST 0xc08 128 #define RK3576_GLB_SRST_SND 0xc0c 129 #define RK3576_GLB_RST_CON 0xc10 130 #define RK3576_GLB_RST_ST 0xc04 131 #define RK3576_SDIO_CON0 0xC24 132 #define RK3576_SDIO_CON1 0xC28 133 #define RK3576_SDMMC_CON0 0xC30 134 #define RK3576_SDMMC_CON1 0xC34 135 136 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) 137 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) 138 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) 139 140 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) 141 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) 142 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) 143 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) 144 145 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) 146 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) 147 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) 148 149 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) 150 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) 151 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) 152 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) 153 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) 154 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) 155 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) 156 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) 157 158 enum { 159 /* CRU_CLK_SEL8_CON */ 160 PCLK_TOP_SEL_SHIFT = 7, 161 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, 162 PCLK_TOP_SEL_100M = 0, 163 PCLK_TOP_SEL_50M, 164 PCLK_TOP_SEL_OSC, 165 166 /* CRU_CLK_SEL9_CON */ 167 ACLK_TOP_SEL_SHIFT = 5, 168 ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT, 169 ACLK_TOP_SEL_GPLL = 0, 170 ACLK_TOP_SEL_CPLL, 171 ACLK_TOP_SEL_AUPLL, 172 ACLK_TOP_DIV_SHIFT = 0, 173 ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT, 174 175 /* CRU_CLK_SEL10_CON */ 176 ACLK_TOP_MID_SEL_SHIFT = 5, 177 ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT, 178 ACLK_TOP_MID_SEL_GPLL = 0, 179 ACLK_TOP_MID_SEL_CPLL, 180 ACLK_TOP_MID_DIV_SHIFT = 0, 181 ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT, 182 183 /* CRU_CLK_SEL19_CON */ 184 HCLK_TOP_SEL_SHIFT = 2, 185 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, 186 HCLK_TOP_SEL_200M = 0, 187 HCLK_TOP_SEL_100M, 188 HCLK_TOP_SEL_50M, 189 HCLK_TOP_SEL_OSC, 190 191 /* CRU_CLK_SEL25_CON */ 192 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 193 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 194 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 195 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 196 197 /* CRU_CLK_SEL26_CON */ 198 CLK_UART_SRC_SEL_SHIFT = 0, 199 CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, 200 CLK_UART_SRC_SEL_GPLL = 0, 201 CLK_UART_SRC_SEL_CPLL, 202 CLK_UART_SRC_SEL_AUPLL, 203 CLK_UART_SRC_SEL_OSC, 204 205 /* CRU_CLK_SEL27_CON */ 206 CLK_UART1_SRC_SEL_SHIFT = 13, 207 CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT, 208 CLK_UART1_SRC_DIV_SHIFT = 5, 209 CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT, 210 211 /* CRU_CLK_SEL30_CON */ 212 CLK_GMAC0_125M_DIV_SHIFT = 10, 213 CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT, 214 215 /* CRU_CLK_SEL31_CON */ 216 CLK_GMAC1_125M_DIV_SHIFT = 0, 217 CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT, 218 219 /* CRU_CLK_SEL55_CON */ 220 ACLK_BUS_ROOT_SEL_SHIFT = 9, 221 ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, 222 ACLK_BUS_ROOT_SEL_GPLL = 0, 223 ACLK_BUS_ROOT_SEL_CPLL, 224 ACLK_BUS_ROOT_DIV_SHIFT = 4, 225 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, 226 PCLK_BUS_ROOT_SEL_SHIFT = 2, 227 PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT, 228 PCLK_BUS_ROOT_SEL_100M = 0, 229 PCLK_BUS_ROOT_SEL_50M, 230 PCLK_BUS_ROOT_SEL_OSC, 231 HCLK_BUS_ROOT_SEL_SHIFT = 0, 232 HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT, 233 HCLK_BUS_ROOT_SEL_200M = 0, 234 HCLK_BUS_ROOT_SEL_100M, 235 HCLK_BUS_ROOT_SEL_50M, 236 HCLK_BUS_ROOT_SEL_OSC, 237 238 /* CRU_CLK_SEL57_CON */ 239 CLK_I2C8_SEL_SHIFT = 14, 240 CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT, 241 CLK_I2C7_SEL_SHIFT = 12, 242 CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT, 243 CLK_I2C6_SEL_SHIFT = 10, 244 CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT, 245 CLK_I2C5_SEL_SHIFT = 8, 246 CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT, 247 CLK_I2C4_SEL_SHIFT = 6, 248 CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT, 249 CLK_I2C3_SEL_SHIFT = 4, 250 CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT, 251 CLK_I2C2_SEL_SHIFT = 2, 252 CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT, 253 CLK_I2C1_SEL_SHIFT = 0, 254 CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT, 255 CLK_I2C_SEL_200M = 0, 256 CLK_I2C_SEL_100M, 257 CLK_I2C_SEL_50M, 258 CLK_I2C_SEL_OSC, 259 260 /* CRU_CLK_SEL58_CON */ 261 CLK_SARADC_SEL_SHIFT = 12, 262 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, 263 CLK_SARADC_SEL_GPLL = 0, 264 CLK_SARADC_SEL_OSC, 265 CLK_SARADC_DIV_SHIFT = 4, 266 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, 267 CLK_I2C9_SEL_SHIFT = 0, 268 CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT, 269 270 /* CRU_CLK_SEL59_CON */ 271 CLK_TSADC_DIV_SHIFT = 0, 272 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, 273 274 /* CRU_CLK_SEL60_CON */ 275 CLK_UART_SEL_SHIFT = 8, 276 CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT, 277 CLK_UART_SEL_GPLL = 0, 278 CLK_UART_SEL_CPLL, 279 CLK_UART_SEL_AUPLL, 280 CLK_UART_SEL_OSC, 281 CLK_UART_SEL_FRAC0, 282 CLK_UART_SEL_FRAC1, 283 CLK_UART_SEL_FRAC2, 284 CLK_UART_DIV_SHIFT = 0, 285 CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT, 286 287 /* CRU_CLK_SEL70_CON */ 288 CLK_SPI0_SEL_SHIFT = 13, 289 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 290 CLK_SPI_SEL_200M = 0, 291 CLK_SPI_SEL_100M, 292 CLK_SPI_SEL_50M, 293 CLK_SPI_SEL_OSC, 294 295 /* CRU_CLK_SEL71_CON */ 296 CLK_PWM1_SEL_SHIFT = 8, 297 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 298 CLK_SPI4_SEL_SHIFT = 6, 299 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, 300 CLK_SPI3_SEL_SHIFT = 4, 301 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 302 CLK_SPI2_SEL_SHIFT = 2, 303 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 304 CLK_SPI1_SEL_SHIFT = 0, 305 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 306 CLK_PWM_SEL_100M = 0, 307 CLK_PWM_SEL_50M, 308 CLK_PWM_SEL_OSC, 309 310 /* CRU_CLK_SEL72_CON */ 311 DCLK_DECOM_SEL_SHIFT = 5, 312 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 313 DCLK_DECOM_SEL_GPLL = 0, 314 DCLK_DECOM_SEL_SPLL, 315 DCLK_DECOM_DIV_SHIFT = 0, 316 DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT, 317 318 /* CRU_CLK_SEL74_CON */ 319 CLK_PWM2_SEL_SHIFT = 6, 320 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 321 322 /* CRU_CLK_SEL89_CON */ 323 CCLK_EMMC_SEL_SHIFT = 14, 324 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, 325 CCLK_EMMC_SEL_GPLL = 0, 326 CCLK_EMMC_SEL_CPLL, 327 CCLK_EMMC_SEL_OSC, 328 CCLK_EMMC_DIV_SHIFT = 8, 329 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, 330 SCLK_FSPI_SEL_SHIFT = 6, 331 SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT, 332 SCLK_FSPI_SEL_GPLL = 0, 333 SCLK_FSPI_SEL_CPLL, 334 SCLK_FSPI_SEL_OSC, 335 SCLK_FSPI_DIV_SHIFT = 0, 336 SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT, 337 338 /* CRU_CLK_SEL90_CON */ 339 BCLK_EMMC_SEL_SHIFT = 0, 340 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, 341 BCLK_EMMC_SEL_200M = 0, 342 BCLK_EMMC_SEL_100M, 343 BCLK_EMMC_SEL_50M, 344 BCLK_EMMC_SEL_OSC, 345 346 /* CRU_CLK_SEL104_CON */ 347 CLK_GMAC1_PTP_SEL_SHIFT = 13, 348 CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT, 349 CLK_GMAC1_PTP_SEL_GPLL = 0, 350 CLK_GMAC1_PTP_SEL_CPLL, 351 CLK_GMAC1_PTP_SEL_REFIN, 352 CLK_GMAC1_PTP_DIV_SHIFT = 8, 353 CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT, 354 CCLK_SDIO_SRC_SEL_SHIFT = 6, 355 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, 356 CCLK_SDIO_SRC_SEL_GPLL = 0, 357 CCLK_SDIO_SRC_SEL_CPLL, 358 CCLK_SDIO_SRC_SEL_OSC, 359 CCLK_SDIO_SRC_DIV_SHIFT = 0, 360 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, 361 362 /* CRU_CLK_SEL105_CON */ 363 CCLK_SDMMC0_SRC_SEL_SHIFT = 13, 364 CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT, 365 CCLK_SDMMC0_SRC_SEL_GPLL = 0, 366 CCLK_SDMMC0_SRC_SEL_CPLL, 367 CCLK_SDMMC0_SRC_SEL_OSC, 368 CCLK_SDMMC0_SRC_DIV_SHIFT = 7, 369 CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT, 370 CLK_GMAC0_PTP_SEL_SHIFT = 5, 371 CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT, 372 CLK_GMAC0_PTP_SEL_GPLL = 0, 373 CLK_GMAC0_PTP_SEL_CPLL, 374 CLK_GMAC0_PTP_SEL_REFIN, 375 CLK_GMAC0_PTP_DIV_SHIFT = 0, 376 CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT, 377 378 /* CRU_CLK_SEL123_CON */ 379 DCLK_EBC_SEL_SHIFT = 12, 380 DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT, 381 DCLK_EBC_SEL_GPLL = 0, 382 DCLK_EBC_SEL_CPLL, 383 DCLK_EBC_SEL_VPLL, 384 DCLK_EBC_SEL_AUPLL, 385 DCLK_EBC_SEL_LPLL, 386 DCLK_EBC_SEL_FRAC_SRC, 387 DCLK_EBC_SEL_OSC, 388 DCLK_EBC_DIV_SHIFT = 3, 389 DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT, 390 DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0, 391 DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT, 392 DCLK_EBC_FRAC_SRC_SEL_GPLL = 0, 393 DCLK_EBC_FRAC_SRC_SEL_CPLL, 394 DCLK_EBC_FRAC_SRC_SEL_VPLL, 395 DCLK_EBC_FRAC_SRC_SEL_AUPLL, 396 DCLK_EBC_FRAC_SRC_SEL_OSC, 397 398 /* CRU_CLK_SEL144_CON */ 399 PCLK_VOP_ROOT_SEL_SHIFT = 12, 400 PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT, 401 PCLK_VOP_ROOT_SEL_100M = 0, 402 PCLK_VOP_ROOT_SEL_50M, 403 PCLK_VOP_ROOT_SEL_OSC, 404 HCLK_VOP_ROOT_SEL_SHIFT = 10, 405 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, 406 HCLK_VOP_ROOT_SEL_200M = 0, 407 HCLK_VOP_ROOT_SEL_100M, 408 HCLK_VOP_ROOT_SEL_50M, 409 HCLK_VOP_ROOT_SEL_OSC, 410 ACLK_VOP_ROOT_SEL_SHIFT = 5, 411 ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, 412 ACLK_VOP_ROOT_SEL_GPLL = 0, 413 ACLK_VOP_ROOT_SEL_CPLL, 414 ACLK_VOP_ROOT_SEL_AUPLL, 415 ACLK_VOP_ROOT_SEL_SPLL, 416 ACLK_VOP_ROOT_SEL_LPLL, 417 ACLK_VOP_ROOT_DIV_SHIFT = 0, 418 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, 419 420 /* CRU_CLK_SEL145_CON */ 421 DCLK0_VOP_SRC_SEL_SHIFT = 8, 422 DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT, 423 DCLK_VOP_SRC_SEL_GPLL = 0, 424 DCLK_VOP_SRC_SEL_CPLL, 425 DCLK_VOP_SRC_SEL_VPLL, 426 DCLK_VOP_SRC_SEL_BPLL, 427 DCLK_VOP_SRC_SEL_LPLL, 428 DCLK0_VOP_SRC_DIV_SHIFT = 0, 429 DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT, 430 431 /* CRU_CLK_SEL147_CON */ 432 DCLK2_VOP_SEL_SHIFT = 13, 433 DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT, 434 DCLK1_VOP_SEL_SHIFT = 12, 435 DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT, 436 DCLK0_VOP_SEL_SHIFT = 11, 437 DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT, 438 439 /* CRU_CLK_SEL149_CON */ 440 ACLK_VO0_ROOT_SEL_SHIFT = 5, 441 ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT, 442 ACLK_VO0_ROOT_SEL_GPLL = 0, 443 ACLK_VO0_ROOT_SEL_CPLL, 444 ACLK_VO0_ROOT_SEL_LPLL, 445 ACLK_VO0_ROOT_SEL_BPLL, 446 ACLK_VO0_ROOT_DIV_SHIFT = 0, 447 ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT, 448 449 /* CRU_CLK_SEL151_CON */ 450 CLK_DSIHOST0_SEL_SHIFT = 7, 451 CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT, 452 CLK_DSIHOST0_SEL_GPLL = 0, 453 CLK_DSIHOST0_SEL_CPLL, 454 CLK_DSIHOST0_SEL_SPLL, 455 CLK_DSIHOST0_SEL_VPLL, 456 CLK_DSIHOST0_SEL_BPLL, 457 CLK_DSIHOST0_SEL_LPLL, 458 CLK_DSIHOST0_DIV_SHIFT = 0, 459 CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT, 460 461 /* PMUCRU_CLK_SEL5_CON */ 462 CLK_PMU1PWM_SEL_SHIFT = 2, 463 CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, 464 465 /* PMUCRU_CLK_SEL6_CON */ 466 CLK_I2C0_SEL_SHIFT = 7, 467 CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT, 468 469 /* PMUCRU_CLK_SEL8_CON */ 470 CLK_UART1_SEL_SHIFT = 0, 471 CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT, 472 CLK_UART1_SEL_TOP = 0, 473 CLK_UART1_SEL_OSC, 474 475 /* LITCRU_CLK_SEL0_CON */ 476 CLK_LITCORE_SEL_SHIFT = 12, 477 CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT, 478 CLK_LITCORE_SEL_LPLL = 0, 479 CLK_LITCORE_SEL_GPLL, 480 CLK_LITCORE_SEL_PVTPLL, 481 CLK_LITCORE_DIV_SHIFT = 7, 482 CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT, 483 484 }; 485 #endif 486