1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3568_H 8 #define _ASM_ARCH_CRU_RK3568_H 9 10 #define MHz 1000000 11 #define KHz 1000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (1008 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (1000 * MHz) 17 #define PPLL_HZ (100 * MHz) 18 19 /* RK3568 pll id */ 20 enum rk3568_pll_id { 21 APLL, 22 DPLL, 23 CPLL, 24 GPLL, 25 NPLL, 26 VPLL, 27 PPLL, 28 HPLL, 29 PLL_COUNT, 30 }; 31 32 struct rk3568_clk_info { 33 unsigned long id; 34 char *name; 35 bool is_cru; 36 }; 37 38 /* Private data for the clock driver - used by rockchip_get_cru() */ 39 struct rk3568_pmuclk_priv { 40 struct rk3568_pmucru *pmucru; 41 ulong ppll_hz; 42 ulong hpll_hz; 43 }; 44 45 struct rk3568_clk_priv { 46 struct rk3568_cru *cru; 47 struct rk3568_grf *grf; 48 ulong ppll_hz; 49 ulong hpll_hz; 50 ulong gpll_hz; 51 ulong cpll_hz; 52 ulong npll_hz; 53 ulong vpll_hz; 54 ulong armclk_hz; 55 ulong armclk_enter_hz; 56 ulong armclk_init_hz; 57 bool sync_kernel; 58 bool set_armclk_rate; 59 }; 60 61 struct rk3568_pll { 62 unsigned int con0; 63 unsigned int con1; 64 unsigned int con2; 65 unsigned int con3; 66 unsigned int con4; 67 unsigned int reserved0[3]; 68 }; 69 70 struct rk3568_pmucru { 71 struct rk3568_pll pll[2];/* Address Offset: 0x0000 */ 72 unsigned int reserved0[16];/* Address Offset: 0x0040 */ 73 unsigned int mode_con00;/* Address Offset: 0x0080 */ 74 unsigned int reserved1[31];/* Address Offset: 0x0084 */ 75 unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */ 76 unsigned int reserved2[22];/* Address Offset: 0x0128 */ 77 unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */ 78 unsigned int reserved3[29];/* Address Offset: 0x018C */ 79 unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */ 80 }; 81 82 check_member(rk3568_pmucru, mode_con00, 0x80); 83 check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200); 84 85 struct rk3568_cru { 86 struct rk3568_pll pll[6]; 87 unsigned int mode_con00;/* Address Offset: 0x00C0 */ 88 unsigned int misc_con[3];/* Address Offset: 0x00C4 */ 89 unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */ 90 unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */ 91 unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */ 92 unsigned int glb_rst_con;/* Address Offset: 0x00DC */ 93 unsigned int glb_rst_st;/* Address Offset: 0x00E0 */ 94 unsigned int reserved0[7];/* Address Offset: 0x00E4 */ 95 unsigned int clksel_con[85]; /* Address Offset: 0x0100 */ 96 unsigned int reserved1[43];/* Address Offset: 0x0254 */ 97 unsigned int clkgate_con[36];/* Address Offset: 0x0300 */ 98 unsigned int reserved2[28]; /* Address Offset: 0x0390 */ 99 unsigned int softrst_con[30];/* Address Offset: 0x0400 */ 100 unsigned int reserved3[2];/* Address Offset: 0x0478 */ 101 unsigned int ssgtbl[32];/* Address Offset: 0x0480 */ 102 unsigned int reserved4[32];/* Address Offset: 0x0500 */ 103 unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */ 104 unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */ 105 unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */ 106 unsigned int emmc_con[2];/* Address Offset: 0x0598 */ 107 }; 108 109 check_member(rk3568_cru, mode_con00, 0xc0); 110 check_member(rk3568_cru, softrst_con[0], 0x400); 111 112 struct pll_rate_table { 113 unsigned long rate; 114 unsigned int fbdiv; 115 unsigned int postdiv1; 116 unsigned int refdiv; 117 unsigned int postdiv2; 118 unsigned int dsmpd; 119 unsigned int frac; 120 }; 121 122 #define RK3568_PMU_MODE 0x80 123 #define RK3568_PMU_PLL_CON(x) ((x) * 0x4) 124 #define RK3568_PLL_CON(x) ((x) * 0x4) 125 #define RK3568_MODE_CON 0xc0 126 127 enum { 128 /* CRU_PMU_CLK_SEL0_CON */ 129 RTC32K_SEL_SHIFT = 6, 130 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 131 RTC32K_SEL_PMUPVTM = 0, 132 RTC32K_SEL_OSC1_32K, 133 RTC32K_SEL_OSC0_DIV32K, 134 135 /* CRU_PMU_CLK_SEL1_CON */ 136 RTC32K_FRAC_NUMERATOR_SHIFT = 16, 137 RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 138 RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 139 RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 140 141 /* CRU_PMU_CLK_SEL2_CON */ 142 PCLK_PDPMU_SEL_SHIFT = 15, 143 PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT, 144 PCLK_PDPMU_SEL_PPLL = 0, 145 PCLK_PDPMU_SEL_GPLL, 146 PCLK_PDPMU_DIV_SHIFT = 0, 147 PCLK_PDPMU_DIV_MASK = 0x1f, 148 149 /* CRU_PMU_CLK_SEL3_CON */ 150 CLK_I2C0_DIV_SHIFT = 0, 151 CLK_I2C0_DIV_MASK = 0x7f, 152 153 /* CRU_PMU_CLK_SEL6_CON */ 154 CLK_PWM0_SEL_SHIFT = 7, 155 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 156 CLK_PWM0_SEL_XIN24M = 0, 157 CLK_PWM0_SEL_PPLL, 158 CLK_PWM0_DIV_SHIFT = 0, 159 CLK_PWM0_DIV_MASK = 0x7f, 160 161 /* CRU_CLK_SEL0_CON */ 162 CLK_CORE_PRE_SEL_SHIFT = 7, 163 CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT, 164 CLK_CORE_PRE_SEL_SRC = 0, 165 CLK_CORE_PRE_SEL_APLL, 166 167 /* CRU_CLK_SEL2_CON */ 168 SCLK_CORE_PRE_SEL_SHIFT = 15, 169 SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT, 170 SCLK_CORE_PRE_SEL_SRC = 0, 171 SCLK_CORE_PRE_SEL_NPLL, 172 SCLK_CORE_SRC_SEL_SHIFT = 8, 173 SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT, 174 SCLK_CORE_SRC_SEL_APLL = 0, 175 SCLK_CORE_SRC_SEL_GPLL, 176 SCLK_CORE_SRC_SEL_NPLL, 177 SCLK_CORE_SRC_DIV_SHIFT = 0, 178 SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT, 179 180 /* CRU_CLK_SEL3_CON */ 181 GICCLK_CORE_DIV_SHIFT = 8, 182 GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT, 183 ATCLK_CORE_DIV_SHIFT = 0, 184 ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT, 185 186 /* CRU_CLK_SEL4_CON */ 187 PERIPHCLK_CORE_PRE_DIV_SHIFT = 8, 188 PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT, 189 PCLK_CORE_PRE_DIV_SHIFT = 0, 190 PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT, 191 192 /* CRU_CLK_SEL5_CON */ 193 ACLK_CORE_NIU2BUS_SEL_SHIFT = 14, 194 ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT, 195 ACLK_CORE_NDFT_DIV_SHIFT = 8, 196 ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT, 197 198 /* CRU_CLK_SEL10_CON */ 199 HCLK_PERIMID_SEL_SHIFT = 6, 200 HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT, 201 HCLK_PERIMID_SEL_150M = 0, 202 HCLK_PERIMID_SEL_100M, 203 HCLK_PERIMID_SEL_75M, 204 HCLK_PERIMID_SEL_24M, 205 ACLK_PERIMID_SEL_SHIFT = 4, 206 ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT, 207 ACLK_PERIMID_SEL_300M = 0, 208 ACLK_PERIMID_SEL_200M, 209 ACLK_PERIMID_SEL_100M, 210 ACLK_PERIMID_SEL_24M, 211 212 /* CRU_CLK_SEL27_CON */ 213 CLK_CRYPTO_PKA_SEL_SHIFT = 6, 214 CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT, 215 CLK_CRYPTO_PKA_SEL_300M = 0, 216 CLK_CRYPTO_PKA_SEL_200M, 217 CLK_CRYPTO_PKA_SEL_100M, 218 CLK_CRYPTO_CORE_SEL_SHIFT = 4, 219 CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT, 220 CLK_CRYPTO_CORE_SEL_200M = 0, 221 CLK_CRYPTO_CORE_SEL_150M, 222 CLK_CRYPTO_CORE_SEL_100M, 223 HCLK_SECURE_FLASH_SEL_SHIFT = 2, 224 HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT, 225 HCLK_SECURE_FLASH_SEL_150M = 0, 226 HCLK_SECURE_FLASH_SEL_100M, 227 HCLK_SECURE_FLASH_SEL_75M, 228 HCLK_SECURE_FLASH_SEL_24M, 229 ACLK_SECURE_FLASH_SEL_SHIFT = 0, 230 ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT, 231 ACLK_SECURE_FLASH_SEL_200M = 0, 232 ACLK_SECURE_FLASH_SEL_150M, 233 ACLK_SECURE_FLASH_SEL_100M, 234 ACLK_SECURE_FLASH_SEL_24M, 235 236 /* CRU_CLK_SEL28_CON */ 237 CCLK_EMMC_SEL_SHIFT = 12, 238 CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT, 239 CCLK_EMMC_SEL_24M = 0, 240 CCLK_EMMC_SEL_200M, 241 CCLK_EMMC_SEL_150M, 242 CCLK_EMMC_SEL_100M, 243 CCLK_EMMC_SEL_50M, 244 CCLK_EMMC_SEL_375K, 245 BCLK_EMMC_SEL_SHIFT = 8, 246 BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, 247 BCLK_EMMC_SEL_200M = 0, 248 BCLK_EMMC_SEL_150M, 249 BCLK_EMMC_SEL_125M, 250 SCLK_SFC_SEL_SHIFT = 4, 251 SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT, 252 SCLK_SFC_SEL_24M = 0, 253 SCLK_SFC_SEL_50M, 254 SCLK_SFC_SEL_75M, 255 SCLK_SFC_SEL_100M, 256 SCLK_SFC_SEL_125M, 257 SCLK_SFC_SEL_150M, 258 NCLK_NANDC_SEL_SHIFT = 0, 259 NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT, 260 NCLK_NANDC_SEL_200M = 0, 261 NCLK_NANDC_SEL_150M, 262 NCLK_NANDC_SEL_100M, 263 NCLK_NANDC_SEL_24M, 264 265 /* CRU_CLK_SEL30_CON */ 266 CLK_SDMMC1_SEL_SHIFT = 12, 267 CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT, 268 CLK_SDMMC0_SEL_SHIFT = 8, 269 CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT, 270 CLK_SDMMC_SEL_24M = 0, 271 CLK_SDMMC_SEL_400M, 272 CLK_SDMMC_SEL_300M, 273 CLK_SDMMC_SEL_100M, 274 CLK_SDMMC_SEL_50M, 275 CLK_SDMMC_SEL_750K, 276 277 /* CRU_CLK_SEL31_CON */ 278 CLK_MAC0_OUT_SEL_SHIFT = 14, 279 CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT, 280 CLK_MAC0_OUT_SEL_125M = 0, 281 CLK_MAC0_OUT_SEL_50M, 282 CLK_MAC0_OUT_SEL_25M, 283 CLK_MAC0_OUT_SEL_24M, 284 CLK_GMAC0_PTP_REF_SEL_SHIFT = 12, 285 CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT, 286 CLK_GMAC0_PTP_REF_SEL_62_5M = 0, 287 CLK_GMAC0_PTP_REF_SEL_100M, 288 CLK_GMAC0_PTP_REF_SEL_50M, 289 CLK_GMAC0_PTP_REF_SEL_24M, 290 CLK_MAC0_2TOP_SEL_SHIFT = 8, 291 CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT, 292 CLK_MAC0_2TOP_SEL_125M = 0, 293 CLK_MAC0_2TOP_SEL_50M, 294 CLK_MAC0_2TOP_SEL_25M, 295 CLK_MAC0_2TOP_SEL_PPLL, 296 RGMII0_CLK_SEL_SHIFT = 4, 297 RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT, 298 RGMII0_CLK_SEL_125M = 0, 299 RGMII0_CLK_SEL_125M_1, 300 RGMII0_CLK_SEL_2_5M, 301 RGMII0_CLK_SEL_25M, 302 RMII0_CLK_SEL_SHIFT = 3, 303 RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT, 304 RMII0_CLK_SEL_2_5M = 0, 305 RMII0_CLK_SEL_25M, 306 RMII0_EXTCLK_SEL_SHIFT = 2, 307 RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT, 308 RMII0_EXTCLK_SEL_MAC0_TOP = 0, 309 RMII0_EXTCLK_SEL_IO, 310 RMII0_MODE_SHIFT = 0, 311 RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT, 312 RMII0_MODE_SEL_RGMII = 0, 313 RMII0_MODE_SEL_RMII, 314 RMII0_MODE_SEL_GMII, 315 316 /* CRU_CLK_SEL32_CON */ 317 CLK_SDMMC2_SEL_SHIFT = 8, 318 CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT, 319 320 /* CRU_CLK_SEL38_CON */ 321 ACLK_VOP_PRE_SEL_SHIFT = 6, 322 ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT, 323 ACLK_VOP_PRE_SEL_CPLL = 0, 324 ACLK_VOP_PRE_SEL_GPLL, 325 ACLK_VOP_PRE_SEL_HPLL, 326 ACLK_VOP_PRE_SEL_VPLL, 327 ACLK_VOP_PRE_DIV_SHIFT = 0, 328 ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT, 329 330 /* CRU_CLK_SEL39_CON */ 331 DCLK0_VOP_SEL_SHIFT = 10, 332 DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT, 333 DCLK_VOP_SEL_HPLL = 0, 334 DCLK_VOP_SEL_VPLL, 335 DCLK_VOP_SEL_GPLL, 336 DCLK_VOP_SEL_CPLL, 337 DCLK0_VOP_DIV_SHIFT = 0, 338 DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT, 339 340 /* CRU_CLK_SEL40_CON */ 341 DCLK1_VOP_SEL_SHIFT = 10, 342 DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT, 343 DCLK1_VOP_DIV_SHIFT = 0, 344 DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT, 345 346 /* CRU_CLK_SEL41_CON */ 347 DCLK2_VOP_SEL_SHIFT = 10, 348 DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT, 349 DCLK2_VOP_DIV_SHIFT = 0, 350 DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT, 351 352 /* CRU_CLK_SEL43_CON */ 353 DCLK_EBC_SEL_SHIFT = 6, 354 DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT, 355 DCLK_EBC_SEL_GPLL_400M = 0, 356 DCLK_EBC_SEL_CPLL_333M, 357 DCLK_EBC_SEL_GPLL_200M, 358 359 /* CRU_CLK_SEL50_CON */ 360 PCLK_BUS_SEL_SHIFT = 4, 361 PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT, 362 PCLK_BUS_SEL_100M = 0, 363 PCLK_BUS_SEL_75M, 364 PCLK_BUS_SEL_50M, 365 PCLK_BUS_SEL_24M, 366 ACLK_BUS_SEL_SHIFT = 0, 367 ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT, 368 ACLK_BUS_SEL_200M = 0, 369 ACLK_BUS_SEL_150M, 370 ACLK_BUS_SEL_100M, 371 ACLK_BUS_SEL_24M, 372 373 /* CRU_CLK_SEL51_CON */ 374 CLK_TSADC_DIV_SHIFT = 8, 375 CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT, 376 CLK_TSADC_TSEN_SEL_SHIFT = 4, 377 CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT, 378 CLK_TSADC_TSEN_SEL_24M = 0, 379 CLK_TSADC_TSEN_SEL_100M, 380 CLK_TSADC_TSEN_SEL_CPLL_100M, 381 CLK_TSADC_TSEN_DIV_SHIFT = 0, 382 CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT, 383 384 /* CRU_CLK_SEL71_CON */ 385 CLK_I2C_SEL_SHIFT = 8, 386 CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT, 387 CLK_I2C_SEL_200M = 0, 388 CLK_I2C_SEL_100M, 389 CLK_I2C_SEL_24M, 390 CLK_I2C_SEL_CPLL_100M, 391 392 /* CRU_CLK_SEL72_CON */ 393 CLK_PWM3_SEL_SHIFT = 12, 394 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT, 395 CLK_PWM2_SEL_SHIFT = 10, 396 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, 397 CLK_PWM1_SEL_SHIFT = 8, 398 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, 399 CLK_PWM_SEL_100M = 0, 400 CLK_PWM_SEL_24M, 401 CLK_PWM_SEL_CPLL_100M, 402 CLK_SPI3_SEL_SHIFT = 6, 403 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, 404 CLK_SPI2_SEL_SHIFT = 4, 405 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, 406 CLK_SPI1_SEL_SHIFT = 2, 407 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, 408 CLK_SPI0_SEL_SHIFT = 0, 409 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, 410 CLK_SPI_SEL_200M = 0, 411 CLK_SPI_SEL_24M, 412 CLK_SPI_SEL_CPLL_100M, 413 414 /* CRU_CLK_SEL73_CON */ 415 PCLK_TOP_SEL_SHIFT = 12, 416 PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, 417 PCLK_TOP_SEL_100M = 0, 418 PCLK_TOP_SEL_75M, 419 PCLK_TOP_SEL_50M, 420 PCLK_TOP_SEL_24M, 421 HCLK_TOP_SEL_SHIFT = 8, 422 HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, 423 HCLK_TOP_SEL_150M = 0, 424 HCLK_TOP_SEL_100M, 425 HCLK_TOP_SEL_75M, 426 HCLK_TOP_SEL_24M, 427 ACLK_TOP_LOW_SEL_SHIFT = 4, 428 ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT, 429 ACLK_TOP_LOW_SEL_400M = 0, 430 ACLK_TOP_LOW_SEL_300M, 431 ACLK_TOP_LOW_SEL_200M, 432 ACLK_TOP_LOW_SEL_24M, 433 ACLK_TOP_HIGH_SEL_SHIFT = 0, 434 ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT, 435 ACLK_TOP_HIGH_SEL_500M = 0, 436 ACLK_TOP_HIGH_SEL_400M, 437 ACLK_TOP_HIGH_SEL_300M, 438 ACLK_TOP_HIGH_SEL_24M, 439 440 /* CRU_CLK_SEL79_CON */ 441 CPLL_333M_DIV_SHIFT = 0, 442 CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT, 443 }; 444 #endif 445