1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * Author: Andy Yan <andy.yan@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3368_H 7 #define _ASM_ARCH_CRU_RK3368_H 8 9 #include <common.h> 10 11 12 /* RK3368 clock numbers */ 13 enum rk3368_pll_id { 14 APLLB, 15 APLLL, 16 DPLL, 17 CPLL, 18 GPLL, 19 NPLL, 20 PLL_COUNT, 21 }; 22 23 struct rk3368_clk_info { 24 unsigned long id; 25 char *name; 26 bool is_cru; 27 }; 28 29 struct rk3368_cru { 30 struct rk3368_pll { 31 unsigned int con0; 32 unsigned int con1; 33 unsigned int con2; 34 unsigned int con3; 35 } pll[6]; 36 unsigned int reserved[0x28]; 37 unsigned int clksel_con[56]; 38 unsigned int reserved1[8]; 39 unsigned int clkgate_con[25]; 40 unsigned int reserved2[7]; 41 unsigned int glb_srst_fst_val; 42 unsigned int glb_srst_snd_val; 43 unsigned int reserved3[0x1e]; 44 unsigned int softrst_con[15]; 45 unsigned int reserved4[0x11]; 46 unsigned int misc_con; 47 unsigned int glb_cnt_th; 48 unsigned int glb_rst_con; 49 unsigned int glb_rst_st; 50 unsigned int reserved5[0x1c]; 51 unsigned int sdmmc_con[2]; 52 unsigned int sdio0_con[2]; 53 unsigned int sdio1_con[2]; 54 unsigned int emmc_con[2]; 55 }; 56 check_member(rk3368_cru, emmc_con[1], 0x41c); 57 58 struct rk3368_clk_priv { 59 struct rk3368_cru *cru; 60 }; 61 62 enum { 63 /* PLL CON0 */ 64 PLL_NR_SHIFT = 8, 65 PLL_NR_MASK = GENMASK(13, 8), 66 PLL_OD_SHIFT = 0, 67 PLL_OD_MASK = GENMASK(3, 0), 68 69 /* PLL CON1 */ 70 PLL_LOCK_STA = BIT(31), 71 PLL_NF_SHIFT = 0, 72 PLL_NF_MASK = GENMASK(12, 0), 73 74 /* PLL CON2 */ 75 PLL_BWADJ_SHIFT = 0, 76 PLL_BWADJ_MASK = GENMASK(11, 0), 77 78 /* PLL CON3 */ 79 PLL_MODE_SHIFT = 8, 80 PLL_MODE_MASK = GENMASK(9, 8), 81 PLL_MODE_SLOW = 0, 82 PLL_MODE_NORMAL = 1, 83 PLL_MODE_DEEP_SLOW = 3, 84 PLL_RESET_SHIFT = 5, 85 PLL_RESET = 1, 86 PLL_RESET_MASK = GENMASK(5, 5), 87 88 /* CLKSEL1CON */ 89 CORE_ACLK_DIV_SHIFT = 0, 90 CORE_ACLK_DIV_MASK = 0x1f << CORE_ACLK_DIV_SHIFT, 91 CORE_DBG_DIV_SHIFT = 8, 92 CORE_DBG_DIV_MASK = 0x1f << CORE_DBG_DIV_SHIFT, 93 94 CORE_CLK_PLL_SEL_SHIFT = 7, 95 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 96 CORE_CLK_PLL_SEL_APLL = 0, 97 CORE_CLK_PLL_SEL_GPLL, 98 CORE_DIV_CON_SHIFT = 0, 99 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 100 101 /* CLKSEL8CON */ 102 PCLK_BUS_DIV_CON_SHIFT = 12, 103 PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, 104 HCLK_BUS_DIV_CON_SHIFT = 8, 105 HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, 106 CLK_BUS_PLL_SEL_CPLL = 0, 107 CLK_BUS_PLL_SEL_GPLL = 1, 108 CLK_BUS_PLL_SEL_SHIFT = 7, 109 CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 110 ACLK_BUS_DIV_CON_SHIFT = 0, 111 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 112 113 /* CLKSEL9CON */ 114 PCLK_PERI_DIV_CON_SHIFT = 12, 115 PCLK_PERI_DIV_CON_MASK = 0x3 << PCLK_PERI_DIV_CON_SHIFT, 116 HCLK_PERI_DIV_CON_SHIFT = 8, 117 HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, 118 CLK_PERI_PLL_SEL_CPLL = 0, 119 CLK_PERI_PLL_SEL_GPLL, 120 CLK_PERI_PLL_SEL_SHIFT = 7, 121 CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 122 ACLK_PERI_DIV_CON_SHIFT = 0, 123 ACLK_PERI_DIV_CON_MASK = 0x1f, 124 125 /* CLKSEL12_CON */ 126 MCU_STCLK_DIV_SHIFT = 8, 127 MCU_STCLK_DIV_MASK = GENMASK(10, 8), 128 MCU_PLL_SEL_SHIFT = 7, 129 MCU_PLL_SEL_MASK = BIT(7), 130 MCU_PLL_SEL_CPLL = 0, 131 MCU_PLL_SEL_GPLL = 1, 132 MCU_CLK_DIV_SHIFT = 0, 133 MCU_CLK_DIV_MASK = GENMASK(4, 0), 134 135 /* CLKSEL19_CON */ 136 ACLK_VOP_PLL_SEL_SHIFT = 6, 137 ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6), 138 ACLK_VOP_PLL_SEL_CPLL = 0, 139 ACLK_VOP_PLL_SEL_GPLL = 1, 140 ACLK_VOP_DIV_SHIFT = 0, 141 ACLK_VOP_DIV_MASK = GENMASK(4, 0), 142 143 /* CLKSEL20_CON */ 144 DCLK_VOP_PLL_SEL_SHIFT = 8, 145 DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8), 146 DCLK_VOP_PLL_SEL_CPLL = 0, 147 DCLK_VOP_PLL_SEL_GPLL = 1, 148 DCLK_VOP_PLL_SEL_NPLL = 2, 149 DCLK_VOP_DIV_SHIFT = 0, 150 DCLK_VOP_DIV_MASK = GENMASK(7, 0), 151 152 /* CLKSEL_CON25 */ 153 CLK_SARADC_DIV_CON_SHIFT = 8, 154 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 155 CLK_SARADC_DIV_CON_WIDTH = 8, 156 157 /* CLKSEL43_CON */ 158 GMAC_DIV_CON_SHIFT = 0x0, 159 GMAC_DIV_CON_MASK = GENMASK(4, 0), 160 GMAC_PLL_SHIFT = 6, 161 GMAC_PLL_MASK = GENMASK(7, 6), 162 GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT), 163 GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT), 164 GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT), 165 GMAC_MUX_SEL_EXTCLK = BIT(8), 166 167 /* CLKSEL51_CON */ 168 MMC_PLL_SEL_SHIFT = 8, 169 MMC_PLL_SEL_MASK = GENMASK(9, 8), 170 MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), 171 MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), 172 MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), 173 MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), 174 MMC_CLK_DIV_SHIFT = 0, 175 MMC_CLK_DIV_MASK = GENMASK(6, 0), 176 177 /* SOFTRST1_CON */ 178 MCU_PO_SRST_MASK = BIT(13), 179 MCU_SYS_SRST_MASK = BIT(12), 180 DMA1_SRST_REQ = BIT(2), 181 182 /* SOFTRST4_CON */ 183 DMA2_SRST_REQ = BIT(0), 184 185 /* GLB_RST_CON */ 186 PMU_GLB_SRST_CTRL_SHIFT = 2, 187 PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), 188 PMU_RST_BY_FST_GLB_SRST = 0, 189 PMU_RST_BY_SND_GLB_SRST = 1, 190 PMU_RST_DISABLE = 2, 191 WDT_GLB_SRST_CTRL_SHIFT = 1, 192 WDT_GLB_SRST_CTRL_MASK = BIT(1), 193 WDT_TRIGGER_SND_GLB_SRST = 0, 194 WDT_TRIGGER_FST_GLB_SRST = 1, 195 TSADC_GLB_SRST_CTRL_SHIFT = 0, 196 TSADC_GLB_SRST_CTRL_MASK = BIT(0), 197 TSADC_TRIGGER_SND_GLB_SRST = 0, 198 TSADC_TRIGGER_FST_GLB_SRST = 1, 199 200 }; 201 #endif 202