xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h (revision d1dcf8527ececd1595d7ae6dc56c19bbcf0c537d) 
1*d1dcf852SAndy Yan /*
2*d1dcf852SAndy Yan  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3*d1dcf852SAndy Yan  * Author: Andy Yan <andy.yan@rock-chips.com>
4*d1dcf852SAndy Yan  * SPDX-License-Identifier:     GPL-2.0+
5*d1dcf852SAndy Yan  */
6*d1dcf852SAndy Yan #ifndef _ASM_ARCH_CRU_RK3368_H
7*d1dcf852SAndy Yan #define _ASM_ARCH_CRU_RK3368_H
8*d1dcf852SAndy Yan 
9*d1dcf852SAndy Yan #include <common.h>
10*d1dcf852SAndy Yan 
11*d1dcf852SAndy Yan 
12*d1dcf852SAndy Yan /* RK3368 clock numbers */
13*d1dcf852SAndy Yan enum rk3368_pll_id {
14*d1dcf852SAndy Yan 	APLLB,
15*d1dcf852SAndy Yan 	APLLL,
16*d1dcf852SAndy Yan 	DPLL,
17*d1dcf852SAndy Yan 	CPLL,
18*d1dcf852SAndy Yan 	GPLL,
19*d1dcf852SAndy Yan 	NPLL,
20*d1dcf852SAndy Yan 	PLL_COUNT,
21*d1dcf852SAndy Yan };
22*d1dcf852SAndy Yan 
23*d1dcf852SAndy Yan struct rk3368_cru {
24*d1dcf852SAndy Yan 	struct rk3368_pll {
25*d1dcf852SAndy Yan 		unsigned int con0;
26*d1dcf852SAndy Yan 		unsigned int con1;
27*d1dcf852SAndy Yan 		unsigned int con2;
28*d1dcf852SAndy Yan 		unsigned int con3;
29*d1dcf852SAndy Yan 	} pll[6];
30*d1dcf852SAndy Yan 	unsigned int reserved[0x28];
31*d1dcf852SAndy Yan 	unsigned int clksel_con[56];
32*d1dcf852SAndy Yan 	unsigned int reserved1[8];
33*d1dcf852SAndy Yan 	unsigned int clkgate_con[25];
34*d1dcf852SAndy Yan 	unsigned int reserved2[7];
35*d1dcf852SAndy Yan 	unsigned int glb_srst_fst_val;
36*d1dcf852SAndy Yan 	unsigned int glb_srst_snd_val;
37*d1dcf852SAndy Yan 	unsigned int reserved3[0x1e];
38*d1dcf852SAndy Yan 	unsigned int softrst_con[15];
39*d1dcf852SAndy Yan 	unsigned int reserved4[0x11];
40*d1dcf852SAndy Yan 	unsigned int misc_con;
41*d1dcf852SAndy Yan 	unsigned int glb_cnt_th;
42*d1dcf852SAndy Yan 	unsigned int glb_rst_con;
43*d1dcf852SAndy Yan 	unsigned int glb_rst_st;
44*d1dcf852SAndy Yan 	unsigned int reserved5[0x1c];
45*d1dcf852SAndy Yan 	unsigned int sdmmc_con[2];
46*d1dcf852SAndy Yan 	unsigned int sdio0_con[2];
47*d1dcf852SAndy Yan 	unsigned int sdio1_con[2];
48*d1dcf852SAndy Yan 	unsigned int emmc_con[2];
49*d1dcf852SAndy Yan };
50*d1dcf852SAndy Yan check_member(rk3368_cru, emmc_con[1], 0x41c);
51*d1dcf852SAndy Yan 
52*d1dcf852SAndy Yan struct rk3368_clk_priv {
53*d1dcf852SAndy Yan 	struct rk3368_cru *cru;
54*d1dcf852SAndy Yan 	ulong rate;
55*d1dcf852SAndy Yan 	bool has_bwadj;
56*d1dcf852SAndy Yan };
57*d1dcf852SAndy Yan 
58*d1dcf852SAndy Yan enum {
59*d1dcf852SAndy Yan 	/* PLL CON0 */
60*d1dcf852SAndy Yan 	PLL_NR_SHIFT			= 8,
61*d1dcf852SAndy Yan 	PLL_NR_MASK			= GENMASK(13, 8),
62*d1dcf852SAndy Yan 	PLL_OD_SHIFT			= 0,
63*d1dcf852SAndy Yan 	PLL_OD_MASK			= GENMASK(3, 0),
64*d1dcf852SAndy Yan 
65*d1dcf852SAndy Yan 	/* PLL CON1 */
66*d1dcf852SAndy Yan 	PLL_LOCK_STA			= BIT(31),
67*d1dcf852SAndy Yan 	PLL_NF_SHIFT			= 0,
68*d1dcf852SAndy Yan 	PLL_NF_MASK			= GENMASK(12, 0),
69*d1dcf852SAndy Yan 
70*d1dcf852SAndy Yan 	/* PLL CON2 */
71*d1dcf852SAndy Yan 	PLL_BWADJ_SHIFT			= 0,
72*d1dcf852SAndy Yan 	PLL_BWADJ_MASK			= GENMASK(11, 0),
73*d1dcf852SAndy Yan 
74*d1dcf852SAndy Yan 	/* PLL CON3 */
75*d1dcf852SAndy Yan 	PLL_MODE_SHIFT			= 8,
76*d1dcf852SAndy Yan 	PLL_MODE_MASK			= GENMASK(9, 8),
77*d1dcf852SAndy Yan 	PLL_MODE_SLOW			= 0,
78*d1dcf852SAndy Yan 	PLL_MODE_NORMAL			= 1,
79*d1dcf852SAndy Yan 	PLL_MODE_DEEP_SLOW		= 3,
80*d1dcf852SAndy Yan 	PLL_RESET_SHIFT			= 5,
81*d1dcf852SAndy Yan 	PLL_RESET			= 1,
82*d1dcf852SAndy Yan 	PLL_RESET_MASK			= GENMASK(5, 5),
83*d1dcf852SAndy Yan 
84*d1dcf852SAndy Yan 	/* CLKSEL12_CON */
85*d1dcf852SAndy Yan 	MCU_STCLK_DIV_SHIFT		= 8,
86*d1dcf852SAndy Yan 	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
87*d1dcf852SAndy Yan 	MCU_PLL_SEL_SHIFT		= 7,
88*d1dcf852SAndy Yan 	MCU_PLL_SEL_MASK		= BIT(7),
89*d1dcf852SAndy Yan 	MCU_PLL_SEL_CPLL		= 0,
90*d1dcf852SAndy Yan 	MCU_PLL_SEL_GPLL		= 1,
91*d1dcf852SAndy Yan 	MCU_CLK_DIV_SHIFT		= 0,
92*d1dcf852SAndy Yan 	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
93*d1dcf852SAndy Yan 
94*d1dcf852SAndy Yan 	/* CLKSEL51_CON */
95*d1dcf852SAndy Yan 	MMC_PLL_SEL_SHIFT		= 8,
96*d1dcf852SAndy Yan 	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
97*d1dcf852SAndy Yan 	MMC_PLL_SEL_CPLL		= 0,
98*d1dcf852SAndy Yan 	MMC_PLL_SEL_GPLL,
99*d1dcf852SAndy Yan 	MMC_PLL_SEL_USBPHY_480M,
100*d1dcf852SAndy Yan 	MMC_PLL_SEL_24M,
101*d1dcf852SAndy Yan 	MMC_CLK_DIV_SHIFT		= 0,
102*d1dcf852SAndy Yan 	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
103*d1dcf852SAndy Yan 
104*d1dcf852SAndy Yan 	/* SOFTRST1_CON */
105*d1dcf852SAndy Yan 	MCU_PO_SRST_MASK		= BIT(13),
106*d1dcf852SAndy Yan 	MCU_SYS_SRST_MASK		= BIT(12),
107*d1dcf852SAndy Yan 
108*d1dcf852SAndy Yan 	/* GLB_RST_CON */
109*d1dcf852SAndy Yan 	PMU_GLB_SRST_CTRL_SHIFT		= 2,
110*d1dcf852SAndy Yan 	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
111*d1dcf852SAndy Yan 	PMU_RST_BY_FST_GLB_SRST 	= 0,
112*d1dcf852SAndy Yan 	PMU_RST_BY_SND_GLB_SRST 	= 1,
113*d1dcf852SAndy Yan 	PMU_RST_DISABLE			= 2,
114*d1dcf852SAndy Yan 	WDT_GLB_SRST_CTRL_SHIFT		= 1,
115*d1dcf852SAndy Yan 	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
116*d1dcf852SAndy Yan 	WDT_TRIGGER_SND_GLB_SRST 	= 0,
117*d1dcf852SAndy Yan 	WDT_TRIGGER_FST_GLB_SRST 	= 1,
118*d1dcf852SAndy Yan 	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
119*d1dcf852SAndy Yan 	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
120*d1dcf852SAndy Yan 	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
121*d1dcf852SAndy Yan 	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
122*d1dcf852SAndy Yan 
123*d1dcf852SAndy Yan };
124*d1dcf852SAndy Yan #endif
125