1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3128_H 8 #define _ASM_ARCH_CRU_RK3128_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (594 * MHz) 17 #define CPLL_HZ (400 * MHz) 18 #define ACLK_BUS_HZ (148500000) 19 #define ACLK_PERI_HZ (148500000) 20 21 /* Private data for the clock driver - used by rockchip_get_cru() */ 22 struct rk3128_clk_priv { 23 struct rk3128_cru *cru; 24 ulong gpll_hz; 25 }; 26 27 struct rk3128_cru { 28 struct rk3128_pll { 29 unsigned int con0; 30 unsigned int con1; 31 unsigned int con2; 32 unsigned int con3; 33 } pll[4]; 34 unsigned int cru_mode_con; 35 unsigned int cru_clksel_con[35]; 36 unsigned int cru_clkgate_con[11]; 37 unsigned int reserved; 38 unsigned int cru_glb_srst_fst_value; 39 unsigned int cru_glb_srst_snd_value; 40 unsigned int reserved1[2]; 41 unsigned int cru_softrst_con[9]; 42 unsigned int cru_misc_con; 43 unsigned int reserved2[2]; 44 unsigned int cru_glb_cnt_th; 45 unsigned int reserved3[3]; 46 unsigned int cru_glb_rst_st; 47 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 48 unsigned int cru_sdmmc_con[2]; 49 unsigned int cru_sdio_con[2]; 50 unsigned int reserved5[2]; 51 unsigned int cru_emmc_con[2]; 52 unsigned int reserved6[4]; 53 unsigned int cru_pll_prg_en; 54 }; 55 check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 56 57 enum rk3128_pll_id { 58 APLL, 59 DPLL, 60 CPLL, 61 GPLL, 62 PLL_COUNT, 63 }; 64 65 struct rk3128_clk_info { 66 unsigned long id; 67 char *name; 68 bool is_cru; 69 }; 70 71 #define RK2928_PLL_CON(x) ((x) * 0x4) 72 #define RK2928_MODE_CON 0x40 73 74 enum { 75 /* CRU_CLK_SEL0_CON */ 76 BUS_PLL_SEL_SHIFT = 13, 77 BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT, 78 BUS_PLL_SEL_CPLL = 0, 79 BUS_PLL_SEL_GPLL, 80 BUS_PLL_SEL_GPLL_DIV2, 81 BUS_PLL_SEL_GPLL_DIV3, 82 ACLK_BUS_DIV_SHIFT = 8, 83 ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 84 CORE_CLK_PLL_SEL_SHIFT = 7, 85 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 86 CORE_CLK_PLL_SEL_APLL = 0, 87 CORE_CLK_PLL_SEL_GPLL_DIV2, 88 CORE_DIV_CON_SHIFT = 0, 89 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 90 91 /* CRU_CLK_SEL1_CON */ 92 PCLK_BUS_DIV_SHIFT = 12, 93 PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT, 94 HCLK_BUS_DIV_SHIFT = 8, 95 HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT, 96 CORE_ACLK_DIV_SHIFT = 4, 97 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 98 CORE_DBG_DIV_SHIFT = 0, 99 CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 100 101 /* CRU_CLK_SEL2_CON */ 102 NANDC_PLL_SEL_SHIFT = 14, 103 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 104 NANDC_PLL_SEL_CPLL = 0, 105 NANDC_PLL_SEL_GPLL, 106 NANDC_CLK_DIV_SHIFT = 8, 107 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 108 PVTM_CLK_DIV_SHIFT = 0, 109 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 110 111 /* CRU_CLKSEL10_CON */ 112 PERI_PLL_SEL_SHIFT = 14, 113 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 114 PERI_PLL_SEL_GPLL = 0, 115 PERI_PLL_SEL_CPLL, 116 PERI_PLL_SEL_GPLL_DIV2, 117 PERI_PLL_SEL_GPLL_DIV3, 118 PCLK_PERI_DIV_SHIFT = 12, 119 PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT, 120 HCLK_PERI_DIV_SHIFT = 8, 121 HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT, 122 ACLK_PERI_DIV_SHIFT = 0, 123 ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 124 125 /* CRU_CLKSEL11_CON */ 126 SFC_PLL_SEL_SHIFT = 14, 127 SFC_PLL_SEL_MASK = 3 << SFC_PLL_SEL_SHIFT, 128 SFC_PLL_SEL_CPLL = 0, 129 SFC_PLL_SEL_GPLL, 130 SFC_CLK_DIV_SHIFT = 8, 131 SFC_CLK_DIV_MASK = 0x1f << SFC_CLK_DIV_SHIFT, 132 MMC0_PLL_SHIFT = 6, 133 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 134 MMC0_SEL_APLL = 0, 135 MMC0_SEL_GPLL, 136 MMC0_SEL_GPLL_DIV2, 137 MMC0_SEL_24M, 138 MMC0_DIV_SHIFT = 0, 139 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 140 141 /* CRU_CLKSEL12_CON */ 142 EMMC_PLL_SHIFT = 14, 143 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 144 EMMC_SEL_APLL = 0, 145 EMMC_SEL_GPLL, 146 EMMC_SEL_GPLL_DIV2, 147 EMMC_SEL_24M, 148 EMMC_DIV_SHIFT = 8, 149 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 150 SDIO_PLL_SHIFT = 6, 151 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 152 SDIO_SEL_APLL = 0, 153 SDIO_SEL_GPLL, 154 SDIO_SEL_GPLL_DIV2, 155 SDIO_SEL_24M, 156 SDIO_DIV_SHIFT = 0, 157 SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 158 159 /* CLKSEL_CON24 */ 160 SARADC_DIV_CON_SHIFT = 8, 161 SARADC_DIV_CON_MASK = GENMASK(15, 8), 162 SARADC_DIV_CON_WIDTH = 8, 163 164 /* CRU_CLKSEL27_CON*/ 165 DCLK_VOP_SEL_SHIFT = 0, 166 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 167 DCLK_VOP_PLL_SEL_CPLL = 0, 168 DCLK_VOP_DIV_CON_SHIFT = 8, 169 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 170 171 /* CRU_CLKSEL31_CON */ 172 VIO0_PLL_SHIFT = 5, 173 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 174 VI00_SEL_CPLL = 0, 175 VIO0_SEL_GPLL, 176 VIO0_DIV_SHIFT = 0, 177 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 178 VIO1_PLL_SHIFT = 13, 179 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 180 VI01_SEL_CPLL = 0, 181 VIO1_SEL_GPLL, 182 VIO1_DIV_SHIFT = 8, 183 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 184 185 /* CRU_SOFTRST5_CON */ 186 DDRCTRL_PSRST_SHIFT = 11, 187 DDRCTRL_SRST_SHIFT = 10, 188 DDRPHY_PSRST_SHIFT = 9, 189 DDRPHY_SRST_SHIFT = 8, 190 }; 191 #endif 192