1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RK3128_H 8 #define _ASM_ARCH_CRU_RK3128_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (594 * MHz) 17 #define ACLK_BUS_HZ (148500000) 18 #define ACLK_PERI_HZ (148500000) 19 20 /* Private data for the clock driver - used by rockchip_get_cru() */ 21 struct rk3128_clk_priv { 22 struct rk3128_cru *cru; 23 ulong gpll_hz; 24 }; 25 26 struct rk3128_cru { 27 struct rk3128_pll { 28 unsigned int con0; 29 unsigned int con1; 30 unsigned int con2; 31 unsigned int con3; 32 } pll[4]; 33 unsigned int cru_mode_con; 34 unsigned int cru_clksel_con[35]; 35 unsigned int cru_clkgate_con[11]; 36 unsigned int reserved; 37 unsigned int cru_glb_srst_fst_value; 38 unsigned int cru_glb_srst_snd_value; 39 unsigned int reserved1[2]; 40 unsigned int cru_softrst_con[9]; 41 unsigned int cru_misc_con; 42 unsigned int reserved2[2]; 43 unsigned int cru_glb_cnt_th; 44 unsigned int reserved3[3]; 45 unsigned int cru_glb_rst_st; 46 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 47 unsigned int cru_sdmmc_con[2]; 48 unsigned int cru_sdio_con[2]; 49 unsigned int reserved5[2]; 50 unsigned int cru_emmc_con[2]; 51 unsigned int reserved6[4]; 52 unsigned int cru_pll_prg_en; 53 }; 54 check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 55 56 enum rk3128_pll_id { 57 APLL, 58 DPLL, 59 CPLL, 60 GPLL, 61 PLL_COUNT, 62 }; 63 64 struct rk3128_clk_info { 65 unsigned long id; 66 char *name; 67 bool is_cru; 68 }; 69 70 #define RK2928_PLL_CON(x) ((x) * 0x4) 71 #define RK2928_MODE_CON 0x40 72 73 enum { 74 /* CRU_CLK_SEL0_CON */ 75 BUS_PLL_SEL_SHIFT = 13, 76 BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT, 77 BUS_PLL_SEL_CPLL = 0, 78 BUS_PLL_SEL_GPLL, 79 BUS_PLL_SEL_GPLL_DIV2, 80 BUS_PLL_SEL_GPLL_DIV3, 81 ACLK_BUS_DIV_SHIFT = 8, 82 ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 83 CORE_CLK_PLL_SEL_SHIFT = 7, 84 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 85 CORE_CLK_PLL_SEL_APLL = 0, 86 CORE_CLK_PLL_SEL_GPLL_DIV2, 87 CORE_DIV_CON_SHIFT = 0, 88 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 89 90 /* CRU_CLK_SEL1_CON */ 91 PCLK_BUS_DIV_SHIFT = 12, 92 PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT, 93 HCLK_BUS_DIV_SHIFT = 8, 94 HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT, 95 CORE_ACLK_DIV_SHIFT = 4, 96 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 97 CORE_DBG_DIV_SHIFT = 0, 98 CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 99 100 /* CRU_CLK_SEL2_CON */ 101 NANDC_PLL_SEL_SHIFT = 14, 102 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 103 NANDC_PLL_SEL_CPLL = 0, 104 NANDC_PLL_SEL_GPLL, 105 NANDC_CLK_DIV_SHIFT = 8, 106 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 107 PVTM_CLK_DIV_SHIFT = 0, 108 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 109 110 /* CRU_CLKSEL10_CON */ 111 PERI_PLL_SEL_SHIFT = 14, 112 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 113 PERI_PLL_SEL_GPLL = 0, 114 PERI_PLL_SEL_CPLL, 115 PERI_PLL_SEL_GPLL_DIV2, 116 PERI_PLL_SEL_GPLL_DIV3, 117 PCLK_PERI_DIV_SHIFT = 12, 118 PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT, 119 HCLK_PERI_DIV_SHIFT = 8, 120 HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT, 121 ACLK_PERI_DIV_SHIFT = 0, 122 ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 123 124 /* CRU_CLKSEL11_CON */ 125 MMC0_PLL_SHIFT = 6, 126 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 127 MMC0_SEL_APLL = 0, 128 MMC0_SEL_GPLL, 129 MMC0_SEL_GPLL_DIV2, 130 MMC0_SEL_24M, 131 MMC0_DIV_SHIFT = 0, 132 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 133 134 /* CRU_CLKSEL12_CON */ 135 EMMC_PLL_SHIFT = 14, 136 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 137 EMMC_SEL_APLL = 0, 138 EMMC_SEL_GPLL, 139 EMMC_SEL_GPLL_DIV2, 140 EMMC_SEL_24M, 141 EMMC_DIV_SHIFT = 8, 142 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 143 SDIO_PLL_SHIFT = 6, 144 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 145 SDIO_SEL_APLL = 0, 146 SDIO_SEL_GPLL, 147 SDIO_SEL_GPLL_DIV2, 148 SDIO_SEL_24M, 149 SDIO_DIV_SHIFT = 0, 150 SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 151 152 /* CLKSEL_CON24 */ 153 SARADC_DIV_CON_SHIFT = 8, 154 SARADC_DIV_CON_MASK = GENMASK(15, 8), 155 SARADC_DIV_CON_WIDTH = 8, 156 157 /* CRU_CLKSEL27_CON*/ 158 DCLK_VOP_SEL_SHIFT = 0, 159 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 160 DCLK_VOP_PLL_SEL_CPLL = 0, 161 DCLK_VOP_DIV_CON_SHIFT = 8, 162 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 163 164 /* CRU_CLKSEL31_CON */ 165 VIO0_PLL_SHIFT = 5, 166 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 167 VI00_SEL_CPLL = 0, 168 VIO0_SEL_GPLL, 169 VIO0_DIV_SHIFT = 0, 170 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 171 VIO1_PLL_SHIFT = 13, 172 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 173 VI01_SEL_CPLL = 0, 174 VIO1_SEL_GPLL, 175 VIO1_DIV_SHIFT = 8, 176 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 177 178 /* CRU_SOFTRST5_CON */ 179 DDRCTRL_PSRST_SHIFT = 11, 180 DDRCTRL_SRST_SHIFT = 10, 181 DDRPHY_PSRST_SHIFT = 9, 182 DDRPHY_SRST_SHIFT = 8, 183 }; 184 #endif 185