1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_CRU_rk1808_H 7 #define _ASM_ARCH_CRU_rk1808_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 #define APLL_HZ (1200 * MHz) 15 #define PCLK_PMU_HZ (100 * MHz) 16 17 /* PX30 pll id */ 18 enum rk1808_pll_id { 19 APLL, 20 DPLL, 21 CPLL, 22 GPLL, 23 NPLL, 24 PPLL, 25 PLL_COUNT, 26 }; 27 28 struct rk1808_clk_info { 29 unsigned long id; 30 char *name; 31 bool is_cru; 32 }; 33 34 /* Private data for the clock driver - used by rockchip_get_cru() */ 35 struct rk1808_clk_priv { 36 struct rk1808_cru *cru; 37 ulong armclk_hz; 38 ulong cpll_hz; 39 ulong gpll_hz; 40 ulong npll_hz; 41 ulong armclk_enter_hz; 42 ulong armclk_init_hz; 43 bool sync_kernel; 44 bool set_armclk_rate; 45 }; 46 47 struct rk1808_pll { 48 unsigned int con0; 49 unsigned int con1; 50 unsigned int con2; 51 unsigned int con3; 52 unsigned int con4; 53 unsigned int reserved0[3]; 54 }; 55 56 struct rk1808_cru { 57 struct rk1808_pll pll[5]; 58 unsigned int mode; 59 unsigned int misc; 60 unsigned int misc1; 61 unsigned int reserved2[1]; 62 unsigned int glb_cnt_th; 63 unsigned int glb_rst_st; 64 unsigned int glb_srst_fst; 65 unsigned int glb_srst_snd; 66 unsigned int glb_rst_con; 67 unsigned int reserved3[7]; 68 unsigned int hwffc_con0; 69 unsigned int reserved4; 70 unsigned int hwffc_th; 71 unsigned int hwffc_intst; 72 unsigned int apll_con0_s; 73 unsigned int apll_con1_s; 74 unsigned int clksel_con0_s; 75 unsigned int reserved5; 76 unsigned int clksel_con[73]; 77 unsigned int reserved6[3]; 78 unsigned int clkgate_con[20]; 79 unsigned int ssgtbl[32]; 80 unsigned int softrst_con[16]; 81 unsigned int reserved7[(0x380 - 0x33c) / 4 - 1]; 82 unsigned int sdmmc_con[2]; 83 unsigned int sdio_con[2]; 84 unsigned int emmc_con[2]; 85 unsigned int reserved8[(0x400 - 0x394) / 4 - 1]; 86 unsigned int autocs_con[10]; 87 unsigned int reserved9[(0x4000 - 0x424) / 4 - 1]; 88 struct rk1808_pll pmu_pll; 89 unsigned int pmu_mode; 90 unsigned int reserved10[(0x4040 - 0x4020) / 4 - 1]; 91 unsigned int pmu_clksel_con[8]; 92 unsigned int reserved11[(0x4080 - 0x405c) / 4 - 1]; 93 unsigned int pmu_clkgate_con[2]; 94 unsigned int reserved12[(0x40c0 - 0x4084) / 4 - 1]; 95 unsigned int pmu_autocs_con[2]; 96 }; 97 98 check_member(rk1808_cru, pmu_autocs_con[0], 0x40c0); 99 100 #define RK1808_PLL_CON(x) ((x) * 0x4) 101 #define RK1808_MODE_CON 0xa0 102 #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000) 103 #define RK1808_PMU_MODE_CON 0x4020 104 105 enum { 106 /* CRU_CLK_SEL0_CON */ 107 CORE_ACLK_DIV_SHIFT = 12, 108 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 109 CORE_DBG_DIV_SHIFT = 8, 110 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 111 CORE_CLK_PLL_SEL_SHIFT = 7, 112 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 113 CORE_CLK_PLL_SEL_APLL = 0, 114 CORE_CLK_PLL_SEL_GPLL, 115 CORE_DIV_CON_SHIFT = 0, 116 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 117 118 /* CRU_CLK_SEL4_CON */ 119 ACLK_VOP_PLL_SEL_GPLL = 0, 120 ACLK_VOP_PLL_SEL_CPLL = 1, 121 ACLK_VOP_PLL_SEL_SHIFT = 7, 122 ACLK_VOP_PLL_SEL_MASK = 1 << ACLK_VOP_PLL_SEL_SHIFT, 123 ACLK_VOP_DIV_CON_SHIFT = 0, 124 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 125 HCLK_VOP_DIV_CON_SHIFT = 8, 126 HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT, 127 128 /* CRU_CLK_SEL5_CON */ 129 DCLK_VOPRAW_SEL_VOPRAW = 0, 130 DCLK_VOPRAW_SEL_VOPRAW_FRAC = 1, 131 DCLK_VOPRAW_SEL_XIN24M = 2, 132 DCLK_VOPRAW_SEL_SHIFT = 14, 133 DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT, 134 DCLK_VOPRAW_PLL_SEL_CPLL = 0, 135 DCLK_VOPRAW_PLL_SEL_GPLL = 1, 136 DCLK_VOPRAW_PLL_SEL_NPLL = 2, 137 DCLK_VOPRAW_PLL_SEL_SHIFT = 10, 138 DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT, 139 DCLK_VOPRAW_DIV_CON_SHIFT = 0, 140 DCLK_VOPRAW_DIV_CON_MASK = 0xff << DCLK_VOPRAW_DIV_CON_SHIFT, 141 142 /* CRU_CLK_SEL7_CON */ 143 DCLK_VOPLITE_SEL_VOPRAW = 0, 144 DCLK_VOPLITE_SEL_VOPRAW_FRAC = 1, 145 DCLK_VOPLITE_SEL_XIN24M = 2, 146 DCLK_VOPLITE_SEL_SHIFT = 14, 147 DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT, 148 DCLK_VOPLITE_PLL_SEL_CPLL = 0, 149 DCLK_VOPLITE_PLL_SEL_GPLL = 1, 150 DCLK_VOPLITE_PLL_SEL_NPLL = 2, 151 DCLK_VOPLITE_PLL_SEL_SHIFT = 10, 152 DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT, 153 DCLK_VOPLITE_DIV_CON_SHIFT = 0, 154 DCLK_VOPLITE_DIV_CON_MASK = 0xff << DCLK_VOPLITE_DIV_CON_SHIFT, 155 156 /* CRU_CLK_SEL19_CON */ 157 CLK_PERI_PLL_SEL_GPLL = 0, 158 CLK_PERI_PLL_SEL_CPLL = 1, 159 CLK_PERI_PLL_SEL_SHIFT = 15, 160 CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 161 LSCLK_PERI_DIV_CON_SHIFT = 8, 162 LSCLK_PERI_DIV_CON_MASK = 0x1f << LSCLK_PERI_DIV_CON_SHIFT, 163 MSCLK_PERI_DIV_CON_SHIFT = 0, 164 MSCLK_PERI_DIV_CON_MASK = 0x1f << MSCLK_PERI_DIV_CON_SHIFT, 165 166 /* CRU_CLKSEL24_CON */ 167 EMMC_PLL_SHIFT = 14, 168 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 169 EMMC_SEL_GPLL = 0, 170 EMMC_SEL_CPLL, 171 EMMC_SEL_NPLL, 172 EMMC_SEL_24M, 173 EMMC_DIV_SHIFT = 0, 174 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 175 176 /* CRU_CLKSEL25_CON */ 177 EMMC_CLK_SEL_SHIFT = 15, 178 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 179 EMMC_CLK_SEL_EMMC = 0, 180 EMMC_CLK_SEL_EMMC_DIV50, 181 EMMC_DIV50_SHIFT = 0, 182 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 183 184 /* CRU_CLKSEL26_CON */ 185 GMAC_PLL_SEL_SHIFT = 14, 186 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 187 GMAC_PLL_SEL_CPLL = 0, 188 GMAC_PLL_SEL_NPLL, 189 GMAC_PLL_SEL_PPLL, 190 CLK_GMAC_DIV_SHIFT = 8, 191 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 192 SFC_PLL_SEL_SHIFT = 7, 193 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 194 SFC_DIV_CON_SHIFT = 0, 195 SFC_DIV_CON_MASK = 0x7f, 196 197 /* CRU_CLK_SEL27_CON */ 198 CLK_BUS_PLL_SEL_GPLL = 0, 199 CLK_BUS_PLL_SEL_CPLL = 1, 200 CLK_BUS_PLL_SEL_SHIFT = 15, 201 CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 202 HSCLK_BUS_DIV_CON_SHIFT = 8, 203 HSCLK_BUS_DIV_CON_MASK = 0x1f << HSCLK_BUS_DIV_CON_SHIFT, 204 RGMII_CLK_SEL_SHIFT = 2, 205 RGMII_CLK_SEL_MASK = 3 << RGMII_CLK_SEL_SHIFT, 206 RGMII_CLK_SEL_125M = 0, 207 RGMII_CLK_SEL_2M = 2, 208 RGMIIC_CLK_SEL_25M = 3, 209 RMII_CLK_SEL_SHIFT = 1, 210 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 211 RMII_EXTCLK_SEL_SHIFT = 0, 212 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 213 RMII_EXTCLK_SEL_INT = 0, 214 RMII_EXTCLK_SEL_EXT, 215 216 /* CRU_CLK_SEL28_CON */ 217 MSCLK_BUS_DIV_CON_SHIFT = 8, 218 MSCLK_BUS_DIV_CON_MASK = 0x1f << MSCLK_BUS_DIV_CON_SHIFT, 219 LSCLK_BUS_DIV_CON_SHIFT = 0, 220 LSCLK_BUS_DIV_CON_MASK = 0x1f << LSCLK_BUS_DIV_CON_SHIFT, 221 222 /* CRU_CLK_SEL29_CON */ 223 CRYPTO_APK_SEL_SHIFT = 15, 224 CRYPTO_APK_PLL_SEL_MASK = 1 << CRYPTO_APK_SEL_SHIFT, 225 CRYPTO_PLL_SEL_GPLL = 0, 226 CRYPTO_PLL_SEL_CPLL, 227 CRYPTO_APK_DIV_SHIFT = 8, 228 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 229 CRYPTO_PLL_SEL_SHIFT = 7, 230 CRYPTO_PLL_SEL_MASK = 1 << CRYPTO_PLL_SEL_SHIFT, 231 CRYPTO_DIV_SHIFT = 0, 232 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 233 234 /* CRU_CLK_SEL59_CON */ 235 CLK_I2C_PLL_SEL_GPLL = 0, 236 CLK_I2C_PLL_SEL_24M, 237 CLK_I2C2_PLL_SEL_SHIFT = 15, 238 CLK_I2C2_DIV_CON_SHIFT = 8, 239 CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT, 240 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 241 CLK_I2C1_PLL_SEL_SHIFT = 7, 242 CLK_I2C1_DIV_CON_SHIFT = 0, 243 CLK_I2C1_DIV_CON_MASK = 0x7f, 244 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 245 246 /* CRU_CLK_SEL60_CON */ 247 CLK_SPI_PLL_SEL_GPLL = 0, 248 CLK_SPI_PLL_SEL_24M, 249 CLK_SPI0_PLL_SEL_SHIFT = 15, 250 CLK_SPI0_DIV_CON_SHIFT = 8, 251 CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT, 252 CLK_SPI0_PLL_SEL_MASK = 1 << CLK_SPI0_PLL_SEL_SHIFT, 253 CLK_I2C3_PLL_SEL_SHIFT = 7, 254 CLK_I2C3_DIV_CON_SHIFT = 0, 255 CLK_I2C3_DIV_CON_MASK = 0x7f, 256 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 257 258 /* CRU_CLK_SEL61_CON */ 259 CLK_SPI2_PLL_SEL_SHIFT = 15, 260 CLK_SPI2_DIV_CON_SHIFT = 8, 261 CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT, 262 CLK_SPI2_PLL_SEL_MASK = 1 << CLK_SPI2_PLL_SEL_SHIFT, 263 CLK_SPI1_PLL_SEL_SHIFT = 7, 264 CLK_SPI1_DIV_CON_SHIFT = 0, 265 CLK_SPI1_DIV_CON_MASK = 0x7f, 266 CLK_SPI1_PLL_SEL_MASK = 1 << CLK_SPI1_PLL_SEL_SHIFT, 267 268 /* CRU_CLK_SEL62_CON */ 269 CLK_TSADC_DIV_CON_SHIFT = 0, 270 CLK_TSADC_DIV_CON_MASK = 0x3ff, 271 272 /* CRU_CLK_SEL63_CON */ 273 CLK_SARADC_DIV_CON_SHIFT = 0, 274 CLK_SARADC_DIV_CON_MASK = 0x3ff, 275 276 /* CRU_CLK_SEL69_CON */ 277 CLK_PWM_PLL_SEL_GPLL = 0, 278 CLK_PWM_PLL_SEL_24M, 279 CLK_PWM1_PLL_SEL_SHIFT = 15, 280 CLK_PWM1_DIV_CON_SHIFT = 8, 281 CLK_PWM1_DIV_CON_MASK = 0x7f << CLK_PWM1_DIV_CON_SHIFT, 282 CLK_PWM1_PLL_SEL_MASK = 1 << CLK_PWM1_PLL_SEL_SHIFT, 283 CLK_PWM0_PLL_SEL_SHIFT = 7, 284 CLK_PWM0_DIV_CON_SHIFT = 0, 285 CLK_PWM0_DIV_CON_MASK = 0x7f, 286 CLK_PWM0_PLL_SEL_MASK = 1 << CLK_PWM0_PLL_SEL_SHIFT, 287 288 /* CRU_CLK_SEL70_CON */ 289 CLK_PWM2_PLL_SEL_SHIFT = 7, 290 CLK_PWM2_DIV_CON_SHIFT = 0, 291 CLK_PWM2_DIV_CON_MASK = 0x7f, 292 CLK_PWM2_PLL_SEL_MASK = 1 << CLK_PWM2_PLL_SEL_SHIFT, 293 294 /* CRU_CLK_SEL71_CON */ 295 CLK_I2C5_PLL_SEL_SHIFT = 15, 296 CLK_I2C5_DIV_CON_SHIFT = 8, 297 CLK_I2C5_DIV_CON_MASK = 0x7f << CLK_I2C5_DIV_CON_SHIFT, 298 CLK_I2C5_PLL_SEL_MASK = 1 << CLK_I2C5_PLL_SEL_SHIFT, 299 CLK_I2C4_PLL_SEL_SHIFT = 7, 300 CLK_I2C4_DIV_CON_SHIFT = 0, 301 CLK_I2C4_DIV_CON_MASK = 0x7f, 302 CLK_I2C4_PLL_SEL_MASK = 1 << CLK_I2C4_PLL_SEL_SHIFT, 303 304 /* CRU_PMU_CLK_SEL7_CON */ 305 CLK_I2C0_PLL_SEL_PPLL = 0, 306 CLK_I2C0_PLL_SEL_SHIFT = 15, 307 CLK_I2C0_DIV_CON_SHIFT = 8, 308 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 309 CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT, 310 311 /* PMUCRU_CLK_SEL0_CON */ 312 PCLK_PMU_DIV_CON_SHIFT = 0, 313 PCLK_PMU_DIV_CON_MASK = 0x1f << PCLK_PMU_DIV_CON_SHIFT, 314 }; 315 #endif 316