1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_CRU_rk1808_H 7 #define _ASM_ARCH_CRU_rk1808_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 #define APLL_HZ (600 * MHz) 15 16 /* PX30 pll id */ 17 enum rk1808_pll_id { 18 APLL, 19 DPLL, 20 CPLL, 21 GPLL, 22 NPLL, 23 PPLL, 24 PLL_COUNT, 25 }; 26 27 struct rk1808_clk_info { 28 unsigned long id; 29 char *name; 30 bool is_cru; 31 }; 32 33 /* Private data for the clock driver - used by rockchip_get_cru() */ 34 struct rk1808_clk_priv { 35 struct rk1808_cru *cru; 36 ulong armclk_hz; 37 ulong cpll_hz; 38 ulong gpll_hz; 39 ulong npll_hz; 40 }; 41 42 struct rk1808_pll { 43 unsigned int con0; 44 unsigned int con1; 45 unsigned int con2; 46 unsigned int con3; 47 unsigned int con4; 48 unsigned int reserved0[3]; 49 }; 50 51 struct rk1808_cru { 52 struct rk1808_pll pll[5]; 53 unsigned int mode; 54 unsigned int misc; 55 unsigned int misc1; 56 unsigned int reserved2[1]; 57 unsigned int glb_cnt_th; 58 unsigned int glb_rst_st; 59 unsigned int glb_srst_fst; 60 unsigned int glb_srst_snd; 61 unsigned int glb_rst_con; 62 unsigned int reserved3[7]; 63 unsigned int hwffc_con0; 64 unsigned int reserved4; 65 unsigned int hwffc_th; 66 unsigned int hwffc_intst; 67 unsigned int apll_con0_s; 68 unsigned int apll_con1_s; 69 unsigned int clksel_con0_s; 70 unsigned int reserved5; 71 unsigned int clksel_con[73]; 72 unsigned int reserved6[3]; 73 unsigned int clkgate_con[20]; 74 unsigned int ssgtbl[32]; 75 unsigned int softrst_con[16]; 76 unsigned int reserved7[(0x380 - 0x33c) / 4 - 1]; 77 unsigned int sdmmc_con[2]; 78 unsigned int sdio_con[2]; 79 unsigned int emmc_con[2]; 80 unsigned int reserved8[(0x400 - 0x394) / 4 - 1]; 81 unsigned int autocs_con[10]; 82 unsigned int reserved9[(0x4000 - 0x424) / 4 - 1]; 83 struct rk1808_pll pmu_pll; 84 unsigned int pmu_mode; 85 unsigned int reserved10[(0x4040 - 0x4020) / 4 - 1]; 86 unsigned int pmu_clksel_con[8]; 87 unsigned int reserved11[(0x4080 - 0x405c) / 4 - 1]; 88 unsigned int pmu_clkgate_con[2]; 89 unsigned int reserved12[(0x40c0 - 0x4084) / 4 - 1]; 90 unsigned int pmu_autocs_con[2]; 91 }; 92 93 check_member(rk1808_cru, pmu_autocs_con[0], 0x40c0); 94 95 #define RK1808_PLL_CON(x) ((x) * 0x4) 96 #define RK1808_MODE_CON 0xa0 97 #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000) 98 #define RK1808_PMU_MODE_CON 0x4020 99 100 enum { 101 /* CRU_CLK_SEL0_CON */ 102 CORE_ACLK_DIV_SHIFT = 12, 103 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 104 CORE_DBG_DIV_SHIFT = 8, 105 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 106 CORE_CLK_PLL_SEL_SHIFT = 7, 107 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 108 CORE_CLK_PLL_SEL_APLL = 0, 109 CORE_CLK_PLL_SEL_GPLL, 110 CORE_DIV_CON_SHIFT = 0, 111 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 112 113 /* CRU_CLK_SEL4_CON */ 114 ACLK_VOP_PLL_SEL_GPLL = 0, 115 ACLK_VOP_PLL_SEL_CPLL = 1, 116 ACLK_VOP_PLL_SEL_SHIFT = 7, 117 ACLK_VOP_PLL_SEL_MASK = 1 << ACLK_VOP_PLL_SEL_SHIFT, 118 ACLK_VOP_DIV_CON_SHIFT = 0, 119 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 120 HCLK_VOP_DIV_CON_SHIFT = 8, 121 HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT, 122 123 /* CRU_CLK_SEL5_CON */ 124 DCLK_VOPRAW_SEL_VOPRAW = 1, 125 DCLK_VOPRAW_SEL_VOPRAW_FRAC = 2, 126 DCLK_VOPRAW_SEL_XIN24M = 3, 127 DCLK_VOPRAW_SEL_SHIFT = 14, 128 DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT, 129 DCLK_VOPRAW_PLL_SEL_CPLL = 0, 130 DCLK_VOPRAW_PLL_SEL_GPLL = 1, 131 DCLK_VOPRAW_PLL_SEL_NPLL = 2, 132 DCLK_VOPRAW_PLL_SEL_SHIFT = 10, 133 DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT, 134 DCLK_VOPRAW_DIV_CON_SHIFT = 0, 135 DCLK_VOPRAW_DIV_CON_MASK = 0xf << DCLK_VOPRAW_DIV_CON_SHIFT, 136 137 /* CRU_CLK_SEL7_CON */ 138 DCLK_VOPLITE_SEL_VOPRAW = 1, 139 DCLK_VOPLITE_SEL_VOPRAW_FRAC = 2, 140 DCLK_VOPLITE_SEL_XIN24M = 3, 141 DCLK_VOPLITE_SEL_SHIFT = 14, 142 DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT, 143 DCLK_VOPLITE_PLL_SEL_CPLL = 0, 144 DCLK_VOPLITE_PLL_SEL_GPLL = 1, 145 DCLK_VOPLITE_PLL_SEL_NPLL = 2, 146 DCLK_VOPLITE_PLL_SEL_SHIFT = 10, 147 DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT, 148 DCLK_VOPLITE_DIV_CON_SHIFT = 0, 149 DCLK_VOPLITE_DIV_CON_MASK = 0xf << DCLK_VOPLITE_DIV_CON_SHIFT, 150 151 /* CRU_CLK_SEL19_CON */ 152 CLK_PERI_PLL_SEL_GPLL = 0, 153 CLK_PERI_PLL_SEL_CPLL = 1, 154 CLK_PERI_PLL_SEL_SHIFT = 15, 155 CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 156 LSCLK_PERI_DIV_CON_SHIFT = 8, 157 LSCLK_PERI_DIV_CON_MASK = 0x1f << LSCLK_PERI_DIV_CON_SHIFT, 158 MSCLK_PERI_DIV_CON_SHIFT = 0, 159 MSCLK_PERI_DIV_CON_MASK = 0x1f << MSCLK_PERI_DIV_CON_SHIFT, 160 161 /* CRU_CLKSEL24_CON */ 162 EMMC_PLL_SHIFT = 14, 163 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 164 EMMC_SEL_GPLL = 0, 165 EMMC_SEL_CPLL, 166 EMMC_SEL_NPLL, 167 EMMC_SEL_24M, 168 EMMC_DIV_SHIFT = 0, 169 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 170 171 /* CRU_CLKSEL25_CON */ 172 EMMC_CLK_SEL_SHIFT = 15, 173 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 174 EMMC_CLK_SEL_EMMC = 0, 175 EMMC_CLK_SEL_EMMC_DIV50, 176 EMMC_DIV50_SHIFT = 0, 177 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 178 179 /* CRU_CLK_SEL27_CON */ 180 CLK_BUS_PLL_SEL_GPLL = 0, 181 CLK_BUS_PLL_SEL_CPLL = 1, 182 CLK_BUS_PLL_SEL_SHIFT = 15, 183 CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 184 HSCLK_BUS_DIV_CON_SHIFT = 8, 185 HSCLK_BUS_DIV_CON_MASK = 0x1f << HSCLK_BUS_DIV_CON_SHIFT, 186 187 /* CRU_CLK_SEL28_CON */ 188 MSCLK_BUS_DIV_CON_SHIFT = 8, 189 MSCLK_BUS_DIV_CON_MASK = 0x1f << MSCLK_BUS_DIV_CON_SHIFT, 190 LSCLK_BUS_DIV_CON_SHIFT = 0, 191 LSCLK_BUS_DIV_CON_MASK = 0x1f << LSCLK_BUS_DIV_CON_SHIFT, 192 193 /* CRU_CLK_SEL59_CON */ 194 CLK_I2C_PLL_SEL_GPLL = 0, 195 CLK_I2C_PLL_SEL_24M, 196 CLK_I2C2_PLL_SEL_SHIFT = 15, 197 CLK_I2C2_DIV_CON_SHIFT = 8, 198 CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT, 199 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 200 CLK_I2C1_PLL_SEL_SHIFT = 7, 201 CLK_I2C1_DIV_CON_SHIFT = 0, 202 CLK_I2C1_DIV_CON_MASK = 0x7f, 203 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 204 205 /* CRU_CLK_SEL60_CON */ 206 CLK_SPI_PLL_SEL_GPLL = 0, 207 CLK_SPI_PLL_SEL_24M, 208 CLK_SPI0_PLL_SEL_SHIFT = 15, 209 CLK_SPI0_DIV_CON_SHIFT = 8, 210 CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT, 211 CLK_SPI0_PLL_SEL_MASK = 1 << CLK_SPI0_PLL_SEL_SHIFT, 212 CLK_I2C3_PLL_SEL_SHIFT = 7, 213 CLK_I2C3_DIV_CON_SHIFT = 0, 214 CLK_I2C3_DIV_CON_MASK = 0x7f, 215 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 216 217 /* CRU_CLK_SEL61_CON */ 218 CLK_SPI2_PLL_SEL_SHIFT = 15, 219 CLK_SPI2_DIV_CON_SHIFT = 8, 220 CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT, 221 CLK_SPI2_PLL_SEL_MASK = 1 << CLK_SPI2_PLL_SEL_SHIFT, 222 CLK_SPI1_PLL_SEL_SHIFT = 7, 223 CLK_SPI1_DIV_CON_SHIFT = 0, 224 CLK_SPI1_DIV_CON_MASK = 0x7f, 225 CLK_SPI1_PLL_SEL_MASK = 1 << CLK_SPI1_PLL_SEL_SHIFT, 226 227 /* CRU_CLK_SEL62_CON */ 228 CLK_TSADC_DIV_CON_SHIFT = 0, 229 CLK_TSADC_DIV_CON_MASK = 0x3ff, 230 231 /* CRU_CLK_SEL63_CON */ 232 CLK_SARADC_DIV_CON_SHIFT = 0, 233 CLK_SARADC_DIV_CON_MASK = 0x3ff, 234 235 /* CRU_CLK_SEL69_CON */ 236 CLK_PWM_PLL_SEL_GPLL = 0, 237 CLK_PWM_PLL_SEL_24M, 238 CLK_PWM1_PLL_SEL_SHIFT = 15, 239 CLK_PWM1_DIV_CON_SHIFT = 8, 240 CLK_PWM1_DIV_CON_MASK = 0x7f << CLK_PWM1_DIV_CON_SHIFT, 241 CLK_PWM1_PLL_SEL_MASK = 1 << CLK_PWM1_PLL_SEL_SHIFT, 242 CLK_PWM0_PLL_SEL_SHIFT = 7, 243 CLK_PWM0_DIV_CON_SHIFT = 0, 244 CLK_PWM0_DIV_CON_MASK = 0x7f, 245 CLK_PWM0_PLL_SEL_MASK = 1 << CLK_PWM0_PLL_SEL_SHIFT, 246 247 /* CRU_CLK_SEL70_CON */ 248 CLK_PWM2_PLL_SEL_SHIFT = 7, 249 CLK_PWM2_DIV_CON_SHIFT = 0, 250 CLK_PWM2_DIV_CON_MASK = 0x7f, 251 CLK_PWM2_PLL_SEL_MASK = 1 << CLK_PWM2_PLL_SEL_SHIFT, 252 253 /* CRU_CLK_SEL71_CON */ 254 CLK_I2C5_PLL_SEL_SHIFT = 15, 255 CLK_I2C5_DIV_CON_SHIFT = 8, 256 CLK_I2C5_DIV_CON_MASK = 0x7f << CLK_I2C5_DIV_CON_SHIFT, 257 CLK_I2C5_PLL_SEL_MASK = 1 << CLK_I2C5_PLL_SEL_SHIFT, 258 CLK_I2C4_PLL_SEL_SHIFT = 7, 259 CLK_I2C4_DIV_CON_SHIFT = 0, 260 CLK_I2C4_DIV_CON_MASK = 0x7f, 261 CLK_I2C4_PLL_SEL_MASK = 1 << CLK_I2C4_PLL_SEL_SHIFT, 262 263 /* CRU_PMU_CLK_SEL7_CON */ 264 CLK_I2C0_PLL_SEL_PPLL = 0, 265 CLK_I2C0_PLL_SEL_SHIFT = 15, 266 CLK_I2C0_DIV_CON_SHIFT = 8, 267 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 268 CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT, 269 }; 270 #endif 271