1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_px30_H 7 #define _ASM_ARCH_CRU_px30_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 17 /* PX30 pll id */ 18 enum px30_pll_id { 19 APLL, 20 DPLL, 21 CPLL, 22 NPLL, 23 GPLL, 24 PLL_COUNT, 25 }; 26 27 struct px30_clk_info { 28 unsigned long id; 29 char *name; 30 bool is_cru; 31 }; 32 33 /* Private data for the clock driver - used by rockchip_get_cru() */ 34 struct px30_clk_priv { 35 struct px30_cru *cru; 36 ulong gpll_hz; 37 ulong armclk_hz; 38 }; 39 40 struct px30_pmuclk_priv { 41 struct px30_pmucru *pmucru; 42 ulong gpll_hz; 43 }; 44 45 struct px30_pll { 46 unsigned int con0; 47 unsigned int con1; 48 unsigned int con2; 49 unsigned int con3; 50 unsigned int con4; 51 unsigned int reserved0[3]; 52 }; 53 54 struct px30_cru { 55 struct px30_pll pll[4]; 56 unsigned int reserved1[8]; 57 unsigned int mode; 58 unsigned int misc; 59 unsigned int reserved2[2]; 60 unsigned int glb_cnt_th; 61 unsigned int glb_rst_st; 62 unsigned int glb_srst_fst; 63 unsigned int glb_srst_snd; 64 unsigned int glb_rst_con; 65 unsigned int reserved3[7]; 66 unsigned int hwffc_con0; 67 unsigned int reserved4; 68 unsigned int hwffc_th; 69 unsigned int hwffc_intst; 70 unsigned int apll_con0_s; 71 unsigned int apll_con1_s; 72 unsigned int clksel_con0_s; 73 unsigned int reserved5; 74 unsigned int clksel_con[60]; 75 unsigned int reserved6[4]; 76 unsigned int clkgate_con[18]; 77 unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; 78 unsigned int ssgtbl[32]; 79 unsigned int softrst_con[12]; 80 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; 81 unsigned int sdmmc_con[2]; 82 unsigned int sdio_con[2]; 83 unsigned int emmc_con[2]; 84 unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; 85 unsigned int autocs_con[8]; 86 }; 87 88 check_member(px30_cru, autocs_con[7], 0x41c); 89 90 struct px30_pmucru { 91 struct px30_pll pll; 92 unsigned int pmu_mode; 93 unsigned int reserved1[7]; 94 unsigned int pmu_clksel_con[6]; 95 unsigned int reserved2[10]; 96 unsigned int pmu_clkgate_con[2]; 97 unsigned int reserved3[14]; 98 unsigned int pmu_autocs_con[2]; 99 }; 100 101 check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); 102 103 struct pll_rate_table { 104 unsigned long rate; 105 unsigned int fbdiv; 106 unsigned int postdiv1; 107 unsigned int refdiv; 108 unsigned int postdiv2; 109 unsigned int dsmpd; 110 unsigned int frac; 111 }; 112 113 struct cpu_rate_table { 114 unsigned long rate; 115 unsigned int aclk_div; 116 unsigned int pclk_div; 117 }; 118 119 enum { 120 /* PLLCON0*/ 121 PLL_BP_SHIFT = 15, 122 PLL_POSTDIV1_SHIFT = 12, 123 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 124 PLL_FBDIV_SHIFT = 0, 125 PLL_FBDIV_MASK = 0xfff, 126 127 /* PLLCON1 */ 128 PLL_PDSEL_SHIFT = 15, 129 PLL_PD1_SHIFT = 14, 130 PLL_PD_SHIFT = 13, 131 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 132 PLL_DSMPD_SHIFT = 12, 133 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 134 PLL_LOCK_STATUS_SHIFT = 10, 135 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 136 PLL_POSTDIV2_SHIFT = 6, 137 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 138 PLL_REFDIV_SHIFT = 0, 139 PLL_REFDIV_MASK = 0x3f, 140 141 /* PLLCON2 */ 142 PLL_FOUT4PHASEPD_SHIFT = 27, 143 PLL_FOUTVCOPD_SHIFT = 26, 144 PLL_FOUTPOSTDIVPD_SHIFT = 25, 145 PLL_DACPD_SHIFT = 24, 146 PLL_FRAC_DIV = 0xffffff, 147 148 /* CRU_MODE */ 149 PLLMUX_FROM_XIN24M = 0, 150 PLLMUX_FROM_PLL, 151 PLLMUX_FROM_RTC32K, 152 USBPHY480M_MODE_SHIFT = 8, 153 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 154 NPLL_MODE_SHIFT = 6, 155 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, 156 DPLL_MODE_SHIFT = 4, 157 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 158 CPLL_MODE_SHIFT = 2, 159 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 160 APLL_MODE_SHIFT = 0, 161 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 162 163 /* CRU_CLK_SEL0_CON */ 164 CORE_ACLK_DIV_SHIFT = 12, 165 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 166 CORE_DBG_DIV_SHIFT = 8, 167 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 168 CORE_CLK_PLL_SEL_SHIFT = 7, 169 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 170 CORE_CLK_PLL_SEL_APLL = 0, 171 CORE_CLK_PLL_SEL_GPLL, 172 CORE_DIV_CON_SHIFT = 0, 173 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 174 175 /* CRU_CLK_SEL3_CON */ 176 ACLK_VO_PLL_SHIFT = 6, 177 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, 178 ACLK_VO_SEL_GPLL = 0, 179 ACLK_VO_SEL_CPLL, 180 ACLK_VO_SEL_NPLL, 181 ACLK_VO_DIV_SHIFT = 0, 182 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, 183 184 /* CRU_CLK_SEL5_CON */ 185 DCLK_VOPB_SEL_SHIFT = 14, 186 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, 187 DCLK_VOPB_SEL_DIVOUT = 0, 188 DCLK_VOPB_SEL_FRACOUT, 189 DCLK_VOPB_SEL_24M, 190 DCLK_VOPB_PLL_SEL_SHIFT = 11, 191 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, 192 DCLK_VOPB_PLL_SEL_CPLL = 0, 193 DCLK_VOPB_PLL_SEL_NPLL, 194 DCLK_VOPB_DIV_SHIFT = 0, 195 DCLK_VOPB_DIV_MASK = 0xff, 196 197 /* CRU_CLK_SEL14_CON */ 198 PERI_PLL_SEL_SHIFT =15, 199 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 200 PERI_PLL_GPLL = 0, 201 PERI_PLL_CPLL, 202 PERI_HCLK_DIV_SHIFT = 8, 203 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 204 PERI_ACLK_DIV_SHIFT = 0, 205 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 206 207 /* CRU_CLKSEL15_CON */ 208 NANDC_CLK_SEL_SHIFT = 15, 209 NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, 210 NANDC_CLK_SEL_NANDC = 0, 211 NANDC_CLK_SEL_NANDC_DIV50, 212 NANDC_DIV50_SHIFT = 8, 213 NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, 214 NANDC_PLL_SHIFT = 6, 215 NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, 216 NANDC_SEL_GPLL = 0, 217 NANDC_SEL_CPLL, 218 NANDC_SEL_NPLL, 219 NANDC_DIV_SHIFT = 0, 220 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 221 222 /* CRU_CLKSEL20_CON */ 223 EMMC_PLL_SHIFT = 14, 224 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 225 EMMC_SEL_GPLL = 0, 226 EMMC_SEL_CPLL, 227 EMMC_SEL_NPLL, 228 EMMC_SEL_24M, 229 EMMC_DIV_SHIFT = 0, 230 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 231 232 /* CRU_CLKSEL21_CON */ 233 EMMC_CLK_SEL_SHIFT = 15, 234 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 235 EMMC_CLK_SEL_EMMC = 0, 236 EMMC_CLK_SEL_EMMC_DIV50, 237 EMMC_DIV50_SHIFT = 0, 238 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 239 240 /* CRU_CLKSEL22_CON */ 241 GMAC_PLL_SEL_SHIFT = 14, 242 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 243 GMAC_PLL_SEL_GPLL = 0, 244 GMAC_PLL_SEL_CPLL, 245 GMAC_PLL_SEL_NPLL, 246 CLK_GMAC_DIV_SHIFT = 8, 247 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 248 SFC_PLL_SEL_SHIFT = 7, 249 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 250 SFC_DIV_CON_SHIFT = 0, 251 SFC_DIV_CON_MASK = 0x7f, 252 253 /* CRU_CLK_SEL23_CON */ 254 BUS_PLL_SEL_SHIFT =15, 255 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, 256 BUS_PLL_SEL_GPLL = 0, 257 BUS_PLL_SEL_CPLL, 258 BUS_ACLK_DIV_SHIFT = 8, 259 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 260 RMII_CLK_SEL_SHIFT = 7, 261 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 262 RMII_CLK_SEL_10M = 0, 263 RMII_CLK_SEL_100M, 264 RMII_EXTCLK_SEL_SHIFT = 6, 265 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 266 RMII_EXTCLK_SEL_INT = 0, 267 RMII_EXTCLK_SEL_EXT, 268 PCLK_GMAC_DIV_SHIFT = 0, 269 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, 270 271 /* CRU_CLK_SEL24_CON */ 272 BUS_PCLK_DIV_SHIFT = 8, 273 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, 274 BUS_HCLK_DIV_SHIFT = 0, 275 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 276 277 /* CRU_CLK_SEL24_CON */ 278 UART2_PLL_SEL_SHIFT = 14, 279 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 280 UART2_PLL_SEL_GPLL = 0, 281 UART2_PLL_SEL_24M, 282 UART2_PLL_SEL_480M, 283 UART2_PLL_SEL_NPLL, 284 UART2_DIV_CON_SHIFT = 0, 285 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, 286 287 /* CRU_CLK_SEL25_CON */ 288 UART2_CLK_SEL_SHIFT = 14, 289 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 290 UART2_CLK_SEL_UART2 = 0, 291 UART2_CLK_SEL_UART2_NP5, 292 UART2_CLK_SEL_UART2_FRAC, 293 UART2_DIVNP5_SHIFT = 0, 294 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, 295 296 /* CRU_CLK_SEL49_CON */ 297 CLK_I2C_PLL_SEL_GPLL = 0, 298 CLK_I2C_PLL_SEL_24M, 299 CLK_I2C_DIV_CON_MASK = 0x7f, 300 CLK_I2C_PLL_SEL_MASK = 1, 301 CLK_I2C1_PLL_SEL_SHIFT = 15, 302 CLK_I2C1_DIV_CON_SHIFT = 8, 303 CLK_I2C0_PLL_SEL_SHIFT = 7, 304 CLK_I2C0_DIV_CON_SHIFT = 0, 305 306 /* CRU_CLK_SEL50_CON */ 307 CLK_I2C3_PLL_SEL_SHIFT = 15, 308 CLK_I2C3_DIV_CON_SHIFT = 8, 309 CLK_I2C2_PLL_SEL_SHIFT = 7, 310 CLK_I2C2_DIV_CON_SHIFT = 0, 311 312 /* CRU_CLK_SEL52_CON */ 313 CLK_PWM_PLL_SEL_GPLL = 0, 314 CLK_PWM_PLL_SEL_24M, 315 CLK_PWM_DIV_CON_MASK = 0x7f, 316 CLK_PWM_PLL_SEL_MASK = 1, 317 CLK_PWM1_PLL_SEL_SHIFT = 15, 318 CLK_PWM1_DIV_CON_SHIFT = 8, 319 CLK_PWM0_PLL_SEL_SHIFT = 7, 320 CLK_PWM0_DIV_CON_SHIFT = 0, 321 322 /* CRU_CLK_SEL53_CON */ 323 CLK_SPI_PLL_SEL_GPLL = 0, 324 CLK_SPI_PLL_SEL_24M, 325 CLK_SPI_DIV_CON_MASK = 0x7f, 326 CLK_SPI_PLL_SEL_MASK = 1, 327 CLK_SPI1_PLL_SEL_SHIFT = 15, 328 CLK_SPI1_DIV_CON_SHIFT = 8, 329 CLK_SPI0_PLL_SEL_SHIFT = 7, 330 CLK_SPI0_DIV_CON_SHIFT = 0, 331 332 /* CRU_CLK_SEL55_CON */ 333 CLK_SARADC_DIV_CON_SHIFT = 0, 334 CLK_SARADC_DIV_CON_MASK = 0x7ff, 335 336 /* CRU_PMU_MODE */ 337 GPLL_MODE_SHIFT = 0, 338 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 339 340 /* CRU_PMU_CLK_SEL0_CON */ 341 CLK_PMU_PCLK_DIV_SHIFT = 0, 342 CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, 343 }; 344 #endif 345