1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_px30_H 7 #define _ASM_ARCH_CRU_px30_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (1200 * MHz) 17 #define NPLL_HZ (1188 * MHz) 18 #define ACLK_BUS_HZ (200 * MHz) 19 #define HCLK_BUS_HZ (150 * MHz) 20 #define PCLK_BUS_HZ (100 * MHz) 21 #define ACLK_PERI_HZ (200 * MHz) 22 #define HCLK_PERI_HZ (150 * MHz) 23 #define PCLK_PMU_HZ (100 * MHz) 24 25 /* PX30 pll id */ 26 enum px30_pll_id { 27 APLL, 28 DPLL, 29 CPLL, 30 NPLL, 31 GPLL, 32 PLL_COUNT, 33 }; 34 35 struct px30_clk_info { 36 unsigned long id; 37 char *name; 38 bool is_cru; 39 }; 40 41 /* Private data for the clock driver - used by rockchip_get_cru() */ 42 struct px30_clk_priv { 43 struct px30_cru *cru; 44 ulong gpll_hz; 45 ulong armclk_hz; 46 }; 47 48 struct px30_pmuclk_priv { 49 struct px30_pmucru *pmucru; 50 ulong gpll_hz; 51 }; 52 53 struct px30_pll { 54 unsigned int con0; 55 unsigned int con1; 56 unsigned int con2; 57 unsigned int con3; 58 unsigned int con4; 59 unsigned int reserved0[3]; 60 }; 61 62 struct px30_cru { 63 struct px30_pll pll[4]; 64 unsigned int reserved1[8]; 65 unsigned int mode; 66 unsigned int misc; 67 unsigned int reserved2[2]; 68 unsigned int glb_cnt_th; 69 unsigned int glb_rst_st; 70 unsigned int glb_srst_fst; 71 unsigned int glb_srst_snd; 72 unsigned int glb_rst_con; 73 unsigned int reserved3[7]; 74 unsigned int hwffc_con0; 75 unsigned int reserved4; 76 unsigned int hwffc_th; 77 unsigned int hwffc_intst; 78 unsigned int apll_con0_s; 79 unsigned int apll_con1_s; 80 unsigned int clksel_con0_s; 81 unsigned int reserved5; 82 unsigned int clksel_con[60]; 83 unsigned int reserved6[4]; 84 unsigned int clkgate_con[18]; 85 unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; 86 unsigned int ssgtbl[32]; 87 unsigned int softrst_con[12]; 88 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; 89 unsigned int sdmmc_con[2]; 90 unsigned int sdio_con[2]; 91 unsigned int emmc_con[2]; 92 unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; 93 unsigned int autocs_con[8]; 94 }; 95 96 check_member(px30_cru, autocs_con[7], 0x41c); 97 98 struct px30_pmucru { 99 struct px30_pll pll; 100 unsigned int pmu_mode; 101 unsigned int reserved1[7]; 102 unsigned int pmu_clksel_con[6]; 103 unsigned int reserved2[10]; 104 unsigned int pmu_clkgate_con[2]; 105 unsigned int reserved3[14]; 106 unsigned int pmu_autocs_con[2]; 107 }; 108 109 check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); 110 111 struct pll_rate_table { 112 unsigned long rate; 113 unsigned int fbdiv; 114 unsigned int postdiv1; 115 unsigned int refdiv; 116 unsigned int postdiv2; 117 unsigned int dsmpd; 118 unsigned int frac; 119 }; 120 121 struct cpu_rate_table { 122 unsigned long rate; 123 unsigned int aclk_div; 124 unsigned int pclk_div; 125 }; 126 127 enum { 128 /* PLLCON0*/ 129 PLL_BP_SHIFT = 15, 130 PLL_POSTDIV1_SHIFT = 12, 131 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 132 PLL_FBDIV_SHIFT = 0, 133 PLL_FBDIV_MASK = 0xfff, 134 135 /* PLLCON1 */ 136 PLL_PDSEL_SHIFT = 15, 137 PLL_PD1_SHIFT = 14, 138 PLL_PD_SHIFT = 13, 139 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 140 PLL_DSMPD_SHIFT = 12, 141 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 142 PLL_LOCK_STATUS_SHIFT = 10, 143 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 144 PLL_POSTDIV2_SHIFT = 6, 145 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 146 PLL_REFDIV_SHIFT = 0, 147 PLL_REFDIV_MASK = 0x3f, 148 149 /* PLLCON2 */ 150 PLL_FOUT4PHASEPD_SHIFT = 27, 151 PLL_FOUTVCOPD_SHIFT = 26, 152 PLL_FOUTPOSTDIVPD_SHIFT = 25, 153 PLL_DACPD_SHIFT = 24, 154 PLL_FRAC_DIV = 0xffffff, 155 156 /* CRU_MODE */ 157 PLLMUX_FROM_XIN24M = 0, 158 PLLMUX_FROM_PLL, 159 PLLMUX_FROM_RTC32K, 160 USBPHY480M_MODE_SHIFT = 8, 161 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 162 NPLL_MODE_SHIFT = 6, 163 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, 164 DPLL_MODE_SHIFT = 4, 165 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 166 CPLL_MODE_SHIFT = 2, 167 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 168 APLL_MODE_SHIFT = 0, 169 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 170 171 /* CRU_CLK_SEL0_CON */ 172 CORE_ACLK_DIV_SHIFT = 12, 173 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 174 CORE_DBG_DIV_SHIFT = 8, 175 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 176 CORE_CLK_PLL_SEL_SHIFT = 7, 177 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 178 CORE_CLK_PLL_SEL_APLL = 0, 179 CORE_CLK_PLL_SEL_GPLL, 180 CORE_DIV_CON_SHIFT = 0, 181 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 182 183 /* CRU_CLK_SEL3_CON */ 184 ACLK_VO_PLL_SHIFT = 6, 185 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, 186 ACLK_VO_SEL_GPLL = 0, 187 ACLK_VO_SEL_CPLL, 188 ACLK_VO_SEL_NPLL, 189 ACLK_VO_DIV_SHIFT = 0, 190 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, 191 192 /* CRU_CLK_SEL5_CON */ 193 DCLK_VOPB_SEL_SHIFT = 14, 194 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, 195 DCLK_VOPB_SEL_DIVOUT = 0, 196 DCLK_VOPB_SEL_FRACOUT, 197 DCLK_VOPB_SEL_24M, 198 DCLK_VOPB_PLL_SEL_SHIFT = 11, 199 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, 200 DCLK_VOPB_PLL_SEL_CPLL = 0, 201 DCLK_VOPB_PLL_SEL_NPLL, 202 DCLK_VOPB_DIV_SHIFT = 0, 203 DCLK_VOPB_DIV_MASK = 0xff, 204 205 /* CRU_CLK_SEL8_CON */ 206 DCLK_VOPL_SEL_SHIFT = 14, 207 DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT, 208 DCLK_VOPL_SEL_DIVOUT = 0, 209 DCLK_VOPL_SEL_FRACOUT, 210 DCLK_VOPL_SEL_24M, 211 DCLK_VOPL_PLL_SEL_SHIFT = 11, 212 DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT, 213 DCLK_VOPL_PLL_SEL_NPLL = 0, 214 DCLK_VOPL_PLL_SEL_CPLL, 215 DCLK_VOPL_DIV_SHIFT = 0, 216 DCLK_VOPL_DIV_MASK = 0xff, 217 218 /* CRU_CLK_SEL14_CON */ 219 PERI_PLL_SEL_SHIFT =15, 220 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 221 PERI_PLL_GPLL = 0, 222 PERI_PLL_CPLL, 223 PERI_HCLK_DIV_SHIFT = 8, 224 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 225 PERI_ACLK_DIV_SHIFT = 0, 226 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 227 228 /* CRU_CLKSEL15_CON */ 229 NANDC_CLK_SEL_SHIFT = 15, 230 NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, 231 NANDC_CLK_SEL_NANDC = 0, 232 NANDC_CLK_SEL_NANDC_DIV50, 233 NANDC_DIV50_SHIFT = 8, 234 NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, 235 NANDC_PLL_SHIFT = 6, 236 NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, 237 NANDC_SEL_GPLL = 0, 238 NANDC_SEL_CPLL, 239 NANDC_SEL_NPLL, 240 NANDC_DIV_SHIFT = 0, 241 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 242 243 /* CRU_CLKSEL20_CON */ 244 EMMC_PLL_SHIFT = 14, 245 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 246 EMMC_SEL_GPLL = 0, 247 EMMC_SEL_CPLL, 248 EMMC_SEL_NPLL, 249 EMMC_SEL_24M, 250 EMMC_DIV_SHIFT = 0, 251 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 252 253 /* CRU_CLKSEL21_CON */ 254 EMMC_CLK_SEL_SHIFT = 15, 255 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 256 EMMC_CLK_SEL_EMMC = 0, 257 EMMC_CLK_SEL_EMMC_DIV50, 258 EMMC_DIV50_SHIFT = 0, 259 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 260 261 /* CRU_CLKSEL22_CON */ 262 GMAC_PLL_SEL_SHIFT = 14, 263 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 264 GMAC_PLL_SEL_GPLL = 0, 265 GMAC_PLL_SEL_CPLL, 266 GMAC_PLL_SEL_NPLL, 267 CLK_GMAC_DIV_SHIFT = 8, 268 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 269 SFC_PLL_SEL_SHIFT = 7, 270 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 271 SFC_DIV_CON_SHIFT = 0, 272 SFC_DIV_CON_MASK = 0x7f, 273 274 /* CRU_CLK_SEL23_CON */ 275 BUS_PLL_SEL_SHIFT =15, 276 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, 277 BUS_PLL_SEL_GPLL = 0, 278 BUS_PLL_SEL_CPLL, 279 BUS_ACLK_DIV_SHIFT = 8, 280 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 281 RMII_CLK_SEL_SHIFT = 7, 282 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 283 RMII_CLK_SEL_10M = 0, 284 RMII_CLK_SEL_100M, 285 RMII_EXTCLK_SEL_SHIFT = 6, 286 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 287 RMII_EXTCLK_SEL_INT = 0, 288 RMII_EXTCLK_SEL_EXT, 289 PCLK_GMAC_DIV_SHIFT = 0, 290 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, 291 292 /* CRU_CLK_SEL24_CON */ 293 BUS_PCLK_DIV_SHIFT = 8, 294 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, 295 BUS_HCLK_DIV_SHIFT = 0, 296 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 297 298 /* CRU_CLK_SEL37_CON */ 299 UART2_PLL_SEL_SHIFT = 14, 300 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 301 UART2_PLL_SEL_GPLL = 0, 302 UART2_PLL_SEL_24M, 303 UART2_PLL_SEL_480M, 304 UART2_PLL_SEL_NPLL, 305 UART2_DIV_CON_SHIFT = 0, 306 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, 307 308 /* CRU_CLK_SEL38_CON */ 309 UART2_CLK_SEL_SHIFT = 14, 310 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 311 UART2_CLK_SEL_UART2 = 0, 312 UART2_CLK_SEL_UART2_NP5, 313 UART2_CLK_SEL_UART2_FRAC, 314 UART2_DIVNP5_SHIFT = 0, 315 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, 316 317 /* CRU_CLK_SEL49_CON */ 318 CLK_I2C_PLL_SEL_GPLL = 0, 319 CLK_I2C_PLL_SEL_24M, 320 CLK_I2C_DIV_CON_MASK = 0x7f, 321 CLK_I2C_PLL_SEL_MASK = 1, 322 CLK_I2C1_PLL_SEL_SHIFT = 15, 323 CLK_I2C1_DIV_CON_SHIFT = 8, 324 CLK_I2C0_PLL_SEL_SHIFT = 7, 325 CLK_I2C0_DIV_CON_SHIFT = 0, 326 327 /* CRU_CLK_SEL50_CON */ 328 CLK_I2C3_PLL_SEL_SHIFT = 15, 329 CLK_I2C3_DIV_CON_SHIFT = 8, 330 CLK_I2C2_PLL_SEL_SHIFT = 7, 331 CLK_I2C2_DIV_CON_SHIFT = 0, 332 333 /* CRU_CLK_SEL52_CON */ 334 CLK_PWM_PLL_SEL_GPLL = 0, 335 CLK_PWM_PLL_SEL_24M, 336 CLK_PWM_DIV_CON_MASK = 0x7f, 337 CLK_PWM_PLL_SEL_MASK = 1, 338 CLK_PWM1_PLL_SEL_SHIFT = 15, 339 CLK_PWM1_DIV_CON_SHIFT = 8, 340 CLK_PWM0_PLL_SEL_SHIFT = 7, 341 CLK_PWM0_DIV_CON_SHIFT = 0, 342 343 /* CRU_CLK_SEL53_CON */ 344 CLK_SPI_PLL_SEL_GPLL = 0, 345 CLK_SPI_PLL_SEL_24M, 346 CLK_SPI_DIV_CON_MASK = 0x7f, 347 CLK_SPI_PLL_SEL_MASK = 1, 348 CLK_SPI1_PLL_SEL_SHIFT = 15, 349 CLK_SPI1_DIV_CON_SHIFT = 8, 350 CLK_SPI0_PLL_SEL_SHIFT = 7, 351 CLK_SPI0_DIV_CON_SHIFT = 0, 352 353 /* CRU_CLK_SEL55_CON */ 354 CLK_SARADC_DIV_CON_SHIFT = 0, 355 CLK_SARADC_DIV_CON_MASK = 0x7ff, 356 357 /* CRU_PMU_MODE */ 358 GPLL_MODE_SHIFT = 0, 359 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 360 361 /* CRU_PMU_CLK_SEL0_CON */ 362 CLK_PMU_PCLK_DIV_SHIFT = 0, 363 CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, 364 }; 365 #endif 366