1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_px30_H 7 #define _ASM_ARCH_CRU_px30_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (816 * MHz) 16 #define GPLL_HZ (1200 * MHz) 17 #define CPLL_HZ (594 * MHz) 18 19 #define CORE_PERI_HZ 204000000 20 #define CORE_ACLK_HZ 408000000 21 22 #define BUS_ACLK_HZ 148500000 23 #define BUS_HCLK_HZ 148500000 24 #define BUS_PCLK_HZ 74250000 25 26 #define PERI_ACLK_HZ 148500000 27 #define PERI_HCLK_HZ 148500000 28 #define PERI_PCLK_HZ 74250000 29 30 enum apll_frequencies { 31 APLL_816_MHZ, 32 APLL_600_MHZ, 33 }; 34 35 /* Private data for the clock driver - used by rockchip_get_cru() */ 36 struct px30_clk_priv { 37 struct px30_cru *cru; 38 ulong rate; 39 }; 40 41 /* PX30 pll id */ 42 enum px30_pll_id { 43 APLL, 44 DPLL, 45 CPLL, 46 NPLL, 47 GPLL, 48 PLL_COUNT, 49 }; 50 51 struct px30_cru { 52 struct px30_pll { 53 unsigned int con0; 54 unsigned int con1; 55 unsigned int con2; 56 unsigned int con3; 57 unsigned int con4; 58 unsigned int reserved0[3]; 59 } pll[4]; 60 unsigned int reserved1[8]; 61 unsigned int mode; 62 unsigned int misc; 63 unsigned int reserved2[2]; 64 unsigned int glb_cnt_th; 65 unsigned int glb_rst_st; 66 unsigned int glb_srst_fst; 67 unsigned int glb_srst_snd; 68 unsigned int glb_rst_con; 69 unsigned int reserved3[7]; 70 unsigned int hwffc_con0; 71 unsigned int reserved4; 72 unsigned int hwffc_th; 73 unsigned int hwffc_intst; 74 unsigned int apll_con0_s; 75 unsigned int apll_con1_s; 76 unsigned int clksel_con0_s; 77 unsigned int reserved5; 78 unsigned int clksel_con[60]; 79 unsigned int reserved6[4]; 80 unsigned int clkgate_con[18]; 81 unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; 82 unsigned int ssgtbl[32]; 83 unsigned int softrst_con[12]; 84 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; 85 unsigned int sdmmc_con[2]; 86 unsigned int sdio_con[2]; 87 unsigned int emmc_con[2]; 88 unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; 89 unsigned int autocs_con[8]; 90 unsigned int reserved10[(0xc000 - 0x41c) / 4 - 1]; 91 struct px30_pll gpll; 92 unsigned int pmu_mode; 93 unsigned int reserved11[7]; 94 unsigned int pmu_clksel_con[6]; 95 unsigned int pmu_clkgate_con[2]; 96 unsigned int reserved12[(0xc0c0 - 0xc05c) / 4 - 1]; 97 unsigned int pmu_autocs_con[2]; 98 }; 99 check_member(px30_cru, pmu_autocs_con[1], 0xc0c4); 100 101 struct pll_div { 102 u32 refdiv; 103 u32 fbdiv; 104 u32 postdiv1; 105 u32 postdiv2; 106 u32 frac; 107 }; 108 109 enum { 110 /* PLLCON0*/ 111 PLL_BP_SHIFT = 15, 112 PLL_POSTDIV1_SHIFT = 12, 113 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 114 PLL_FBDIV_SHIFT = 0, 115 PLL_FBDIV_MASK = 0xfff, 116 117 /* PLLCON1 */ 118 PLL_PDSEL_SHIFT = 15, 119 PLL_PD1_SHIFT = 14, 120 PLL_PD_SHIFT = 13, 121 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 122 PLL_DSMPD_SHIFT = 12, 123 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 124 PLL_LOCK_STATUS_SHIFT = 10, 125 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 126 PLL_POSTDIV2_SHIFT = 6, 127 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 128 PLL_REFDIV_SHIFT = 0, 129 PLL_REFDIV_MASK = 0x3f, 130 131 /* PLLCON2 */ 132 PLL_FOUT4PHASEPD_SHIFT = 27, 133 PLL_FOUTVCOPD_SHIFT = 26, 134 PLL_FOUTPOSTDIVPD_SHIFT = 25, 135 PLL_DACPD_SHIFT = 24, 136 PLL_FRAC_DIV = 0xffffff, 137 138 /* CRU_MODE */ 139 PLLMUX_FROM_XIN24M = 0, 140 PLLMUX_FROM_PLL, 141 PLLMUX_FROM_RTC32K, 142 USBPHY480M_MODE_SHIFT = 8, 143 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 144 NPLL_MODE_SHIFT = 6, 145 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, 146 DPLL_MODE_SHIFT = 4, 147 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 148 CPLL_MODE_SHIFT = 2, 149 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 150 APLL_MODE_SHIFT = 0, 151 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 152 153 /* CRU_CLK_SEL0_CON */ 154 CORE_ACLK_DIV_SHIFT = 12, 155 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 156 CORE_DBG_DIV_SHIFT = 8, 157 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 158 CORE_CLK_PLL_SEL_SHIFT = 7, 159 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 160 CORE_CLK_PLL_SEL_APLL = 0, 161 CORE_CLK_PLL_SEL_GPLL, 162 CORE_DIV_CON_SHIFT = 0, 163 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 164 165 /* CRU_CLK_SEL3_CON */ 166 ACLK_VO_PLL_SHIFT = 6, 167 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, 168 ACLK_VO_SEL_GPLL = 0, 169 ACLK_VO_SEL_CPLL, 170 ACLK_VO_SEL_NPLL, 171 ACLK_VO_DIV_SHIFT = 0, 172 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, 173 174 /* CRU_CLK_SEL5_CON */ 175 DCLK_VOPB_SEL_SHIFT = 14, 176 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, 177 DCLK_VOPB_SEL_DIVOUT = 0, 178 DCLK_VOPB_SEL_FRACOUT, 179 DCLK_VOPB_SEL_24M, 180 DCLK_VOPB_PLL_SEL_SHIFT = 11, 181 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, 182 DCLK_VOPB_PLL_SEL_CPLL = 0, 183 DCLK_VOPB_PLL_SEL_NPLL, 184 DCLK_VOPB_DIV_SHIFT = 0, 185 DCLK_VOPB_DIV_MASK = 0xff, 186 187 /* CRU_CLK_SEL14_CON */ 188 PERI_PLL_SEL_SHIFT =15, 189 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 190 PERI_PLL_GPLL = 0, 191 PERI_PLL_CPLL, 192 PERI_HCLK_DIV_SHIFT = 8, 193 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 194 PERI_ACLK_DIV_SHIFT = 0, 195 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 196 197 /* CRU_CLKSEL20_CON */ 198 EMMC_PLL_SHIFT = 14, 199 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 200 EMMC_SEL_GPLL = 0, 201 EMMC_SEL_CPLL, 202 EMMC_SEL_NPLL, 203 EMMC_SEL_24M, 204 EMMC_DIV_SHIFT = 0, 205 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 206 207 /* CRU_CLKSEL21_CON */ 208 EMMC_CLK_SEL_SHIFT = 15, 209 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 210 EMMC_CLK_SEL_EMMC = 0, 211 EMMC_CLK_SEL_EMMC_DIV50, 212 EMMC_DIV50_SHIFT = 0, 213 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 214 215 /* CRU_CLKSEL22_CON */ 216 GMAC_PLL_SEL_SHIFT = 14, 217 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 218 GMAC_PLL_SEL_GPLL = 0, 219 GMAC_PLL_SEL_CPLL, 220 GMAC_PLL_SEL_NPLL, 221 CLK_GMAC_DIV_SHIFT = 8, 222 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 223 SFC_PLL_SEL_SHIFT = 7, 224 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 225 SFC_DIV_CON_SHIFT = 0, 226 SFC_DIV_CON_MASK = 0x7f, 227 228 /* CRU_CLK_SEL23_CON */ 229 BUS_PLL_SEL_SHIFT =15, 230 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, 231 BUS_PLL_SEL_GPLL = 0, 232 BUS_PLL_SEL_CPLL, 233 BUS_ACLK_DIV_SHIFT = 8, 234 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 235 RMII_CLK_SEL_SHIFT = 7, 236 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 237 RMII_CLK_SEL_10M = 0, 238 RMII_CLK_SEL_100M, 239 RMII_EXTCLK_SEL_SHIFT = 6, 240 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 241 RMII_EXTCLK_SEL_INT = 0, 242 RMII_EXTCLK_SEL_EXT, 243 PCLK_GMAC_DIV_SHIFT = 0, 244 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, 245 246 /* CRU_CLK_SEL24_CON */ 247 BUS_PCLK_DIV_SHIFT = 8, 248 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, 249 BUS_HCLK_DIV_SHIFT = 0, 250 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 251 252 /* CRU_CLK_SEL24_CON */ 253 UART2_PLL_SEL_SHIFT = 14, 254 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 255 UART2_PLL_SEL_GPLL = 0, 256 UART2_PLL_SEL_24M, 257 UART2_PLL_SEL_480M, 258 UART2_PLL_SEL_NPLL, 259 UART2_DIV_CON_SHIFT = 0, 260 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, 261 262 /* CRU_CLK_SEL25_CON */ 263 UART2_CLK_SEL_SHIFT = 14, 264 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 265 UART2_CLK_SEL_UART2 = 0, 266 UART2_CLK_SEL_UART2_NP5, 267 UART2_CLK_SEL_UART2_FRAC, 268 UART2_DIVNP5_SHIFT = 0, 269 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, 270 271 /* CRU_CLK_SEL49_CON */ 272 CLK_I2C_PLL_SEL_GPLL = 0, 273 CLK_I2C_PLL_SEL_24M, 274 CLK_I2C_DIV_CON_MASK = 0x7f, 275 CLK_I2C_PLL_SEL_MASK = 1, 276 CLK_I2C1_PLL_SEL_SHIFT = 15, 277 CLK_I2C1_DIV_CON_SHIFT = 8, 278 CLK_I2C0_PLL_SEL_SHIFT = 7, 279 CLK_I2C0_DIV_CON_SHIFT = 0, 280 281 /* CRU_CLK_SEL50_CON */ 282 CLK_I2C3_PLL_SEL_SHIFT = 15, 283 CLK_I2C3_DIV_CON_SHIFT = 8, 284 CLK_I2C2_PLL_SEL_SHIFT = 7, 285 CLK_I2C2_DIV_CON_SHIFT = 0, 286 287 /* CRU_CLK_SEL52_CON */ 288 CLK_PWM_PLL_SEL_GPLL = 0, 289 CLK_PWM_PLL_SEL_24M, 290 CLK_PWM_DIV_CON_MASK = 0x7f, 291 CLK_PWM_PLL_SEL_MASK = 1, 292 CLK_PWM1_PLL_SEL_SHIFT = 15, 293 CLK_PWM1_DIV_CON_SHIFT = 8, 294 CLK_PWM0_PLL_SEL_SHIFT = 7, 295 CLK_PWM0_DIV_CON_SHIFT = 0, 296 297 /* CRU_CLK_SEL53_CON */ 298 CLK_SPI_PLL_SEL_GPLL = 0, 299 CLK_SPI_PLL_SEL_24M, 300 CLK_SPI_DIV_CON_MASK = 0x7f, 301 CLK_SPI_PLL_SEL_MASK = 1, 302 CLK_SPI1_PLL_SEL_SHIFT = 15, 303 CLK_SPI1_DIV_CON_SHIFT = 8, 304 CLK_SPI0_PLL_SEL_SHIFT = 7, 305 CLK_SPI0_DIV_CON_SHIFT = 0, 306 307 /* CRU_CLK_SEL55_CON */ 308 CLK_SARADC_DIV_CON_SHIFT = 0, 309 CLK_SARADC_DIV_CON_MASK = 0x7ff, 310 311 /* CRU_PMU_MODE */ 312 GPLL_MODE_SHIFT = 0, 313 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 314 315 }; 316 #endif 317