1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_px30_H 7 #define _ASM_ARCH_CRU_px30_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (816 * MHz) 16 17 #define CORE_PERI_HZ 204000000 18 #define CORE_ACLK_HZ 408000000 19 20 /* PX30 pll id */ 21 enum px30_pll_id { 22 APLL, 23 DPLL, 24 CPLL, 25 NPLL, 26 GPLL, 27 PLL_COUNT, 28 }; 29 30 struct px30_clk_info { 31 unsigned long id; 32 char *name; 33 bool is_cru; 34 }; 35 36 /* Private data for the clock driver - used by rockchip_get_cru() */ 37 struct px30_clk_priv { 38 struct px30_cru *cru; 39 ulong gpll_hz; 40 }; 41 42 struct px30_pmuclk_priv { 43 struct px30_pmucru *pmucru; 44 ulong gpll_hz; 45 }; 46 47 struct px30_pll { 48 unsigned int con0; 49 unsigned int con1; 50 unsigned int con2; 51 unsigned int con3; 52 unsigned int con4; 53 unsigned int reserved0[3]; 54 }; 55 56 struct px30_cru { 57 struct px30_pll pll[4]; 58 unsigned int reserved1[8]; 59 unsigned int mode; 60 unsigned int misc; 61 unsigned int reserved2[2]; 62 unsigned int glb_cnt_th; 63 unsigned int glb_rst_st; 64 unsigned int glb_srst_fst; 65 unsigned int glb_srst_snd; 66 unsigned int glb_rst_con; 67 unsigned int reserved3[7]; 68 unsigned int hwffc_con0; 69 unsigned int reserved4; 70 unsigned int hwffc_th; 71 unsigned int hwffc_intst; 72 unsigned int apll_con0_s; 73 unsigned int apll_con1_s; 74 unsigned int clksel_con0_s; 75 unsigned int reserved5; 76 unsigned int clksel_con[60]; 77 unsigned int reserved6[4]; 78 unsigned int clkgate_con[18]; 79 unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; 80 unsigned int ssgtbl[32]; 81 unsigned int softrst_con[12]; 82 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; 83 unsigned int sdmmc_con[2]; 84 unsigned int sdio_con[2]; 85 unsigned int emmc_con[2]; 86 unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; 87 unsigned int autocs_con[8]; 88 }; 89 90 check_member(px30_cru, autocs_con[7], 0x41c); 91 92 struct px30_pmucru { 93 struct px30_pll pll; 94 unsigned int pmu_mode; 95 unsigned int reserved1[7]; 96 unsigned int pmu_clksel_con[6]; 97 unsigned int reserved2[10]; 98 unsigned int pmu_clkgate_con[2]; 99 unsigned int reserved3[14]; 100 unsigned int pmu_autocs_con[2]; 101 }; 102 103 check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); 104 105 struct pll_rate_table { 106 unsigned long rate; 107 unsigned int fbdiv; 108 unsigned int postdiv1; 109 unsigned int refdiv; 110 unsigned int postdiv2; 111 unsigned int dsmpd; 112 unsigned int frac; 113 }; 114 115 enum { 116 /* PLLCON0*/ 117 PLL_BP_SHIFT = 15, 118 PLL_POSTDIV1_SHIFT = 12, 119 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 120 PLL_FBDIV_SHIFT = 0, 121 PLL_FBDIV_MASK = 0xfff, 122 123 /* PLLCON1 */ 124 PLL_PDSEL_SHIFT = 15, 125 PLL_PD1_SHIFT = 14, 126 PLL_PD_SHIFT = 13, 127 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 128 PLL_DSMPD_SHIFT = 12, 129 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 130 PLL_LOCK_STATUS_SHIFT = 10, 131 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 132 PLL_POSTDIV2_SHIFT = 6, 133 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 134 PLL_REFDIV_SHIFT = 0, 135 PLL_REFDIV_MASK = 0x3f, 136 137 /* PLLCON2 */ 138 PLL_FOUT4PHASEPD_SHIFT = 27, 139 PLL_FOUTVCOPD_SHIFT = 26, 140 PLL_FOUTPOSTDIVPD_SHIFT = 25, 141 PLL_DACPD_SHIFT = 24, 142 PLL_FRAC_DIV = 0xffffff, 143 144 /* CRU_MODE */ 145 PLLMUX_FROM_XIN24M = 0, 146 PLLMUX_FROM_PLL, 147 PLLMUX_FROM_RTC32K, 148 USBPHY480M_MODE_SHIFT = 8, 149 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 150 NPLL_MODE_SHIFT = 6, 151 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, 152 DPLL_MODE_SHIFT = 4, 153 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 154 CPLL_MODE_SHIFT = 2, 155 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 156 APLL_MODE_SHIFT = 0, 157 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 158 159 /* CRU_CLK_SEL0_CON */ 160 CORE_ACLK_DIV_SHIFT = 12, 161 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 162 CORE_DBG_DIV_SHIFT = 8, 163 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 164 CORE_CLK_PLL_SEL_SHIFT = 7, 165 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 166 CORE_CLK_PLL_SEL_APLL = 0, 167 CORE_CLK_PLL_SEL_GPLL, 168 CORE_DIV_CON_SHIFT = 0, 169 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 170 171 /* CRU_CLK_SEL3_CON */ 172 ACLK_VO_PLL_SHIFT = 6, 173 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, 174 ACLK_VO_SEL_GPLL = 0, 175 ACLK_VO_SEL_CPLL, 176 ACLK_VO_SEL_NPLL, 177 ACLK_VO_DIV_SHIFT = 0, 178 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, 179 180 /* CRU_CLK_SEL5_CON */ 181 DCLK_VOPB_SEL_SHIFT = 14, 182 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, 183 DCLK_VOPB_SEL_DIVOUT = 0, 184 DCLK_VOPB_SEL_FRACOUT, 185 DCLK_VOPB_SEL_24M, 186 DCLK_VOPB_PLL_SEL_SHIFT = 11, 187 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, 188 DCLK_VOPB_PLL_SEL_CPLL = 0, 189 DCLK_VOPB_PLL_SEL_NPLL, 190 DCLK_VOPB_DIV_SHIFT = 0, 191 DCLK_VOPB_DIV_MASK = 0xff, 192 193 /* CRU_CLK_SEL14_CON */ 194 PERI_PLL_SEL_SHIFT =15, 195 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 196 PERI_PLL_GPLL = 0, 197 PERI_PLL_CPLL, 198 PERI_HCLK_DIV_SHIFT = 8, 199 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 200 PERI_ACLK_DIV_SHIFT = 0, 201 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 202 203 /* CRU_CLKSEL15_CON */ 204 NANDC_CLK_SEL_SHIFT = 15, 205 NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, 206 NANDC_CLK_SEL_NANDC = 0, 207 NANDC_CLK_SEL_NANDC_DIV50, 208 NANDC_DIV50_SHIFT = 8, 209 NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, 210 NANDC_PLL_SHIFT = 6, 211 NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, 212 NANDC_SEL_GPLL = 0, 213 NANDC_SEL_CPLL, 214 NANDC_SEL_NPLL, 215 NANDC_DIV_SHIFT = 0, 216 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 217 218 /* CRU_CLKSEL20_CON */ 219 EMMC_PLL_SHIFT = 14, 220 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 221 EMMC_SEL_GPLL = 0, 222 EMMC_SEL_CPLL, 223 EMMC_SEL_NPLL, 224 EMMC_SEL_24M, 225 EMMC_DIV_SHIFT = 0, 226 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 227 228 /* CRU_CLKSEL21_CON */ 229 EMMC_CLK_SEL_SHIFT = 15, 230 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 231 EMMC_CLK_SEL_EMMC = 0, 232 EMMC_CLK_SEL_EMMC_DIV50, 233 EMMC_DIV50_SHIFT = 0, 234 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 235 236 /* CRU_CLKSEL22_CON */ 237 GMAC_PLL_SEL_SHIFT = 14, 238 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 239 GMAC_PLL_SEL_GPLL = 0, 240 GMAC_PLL_SEL_CPLL, 241 GMAC_PLL_SEL_NPLL, 242 CLK_GMAC_DIV_SHIFT = 8, 243 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 244 SFC_PLL_SEL_SHIFT = 7, 245 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 246 SFC_DIV_CON_SHIFT = 0, 247 SFC_DIV_CON_MASK = 0x7f, 248 249 /* CRU_CLK_SEL23_CON */ 250 BUS_PLL_SEL_SHIFT =15, 251 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, 252 BUS_PLL_SEL_GPLL = 0, 253 BUS_PLL_SEL_CPLL, 254 BUS_ACLK_DIV_SHIFT = 8, 255 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 256 RMII_CLK_SEL_SHIFT = 7, 257 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 258 RMII_CLK_SEL_10M = 0, 259 RMII_CLK_SEL_100M, 260 RMII_EXTCLK_SEL_SHIFT = 6, 261 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 262 RMII_EXTCLK_SEL_INT = 0, 263 RMII_EXTCLK_SEL_EXT, 264 PCLK_GMAC_DIV_SHIFT = 0, 265 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, 266 267 /* CRU_CLK_SEL24_CON */ 268 BUS_PCLK_DIV_SHIFT = 8, 269 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, 270 BUS_HCLK_DIV_SHIFT = 0, 271 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 272 273 /* CRU_CLK_SEL24_CON */ 274 UART2_PLL_SEL_SHIFT = 14, 275 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 276 UART2_PLL_SEL_GPLL = 0, 277 UART2_PLL_SEL_24M, 278 UART2_PLL_SEL_480M, 279 UART2_PLL_SEL_NPLL, 280 UART2_DIV_CON_SHIFT = 0, 281 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, 282 283 /* CRU_CLK_SEL25_CON */ 284 UART2_CLK_SEL_SHIFT = 14, 285 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 286 UART2_CLK_SEL_UART2 = 0, 287 UART2_CLK_SEL_UART2_NP5, 288 UART2_CLK_SEL_UART2_FRAC, 289 UART2_DIVNP5_SHIFT = 0, 290 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, 291 292 /* CRU_CLK_SEL49_CON */ 293 CLK_I2C_PLL_SEL_GPLL = 0, 294 CLK_I2C_PLL_SEL_24M, 295 CLK_I2C_DIV_CON_MASK = 0x7f, 296 CLK_I2C_PLL_SEL_MASK = 1, 297 CLK_I2C1_PLL_SEL_SHIFT = 15, 298 CLK_I2C1_DIV_CON_SHIFT = 8, 299 CLK_I2C0_PLL_SEL_SHIFT = 7, 300 CLK_I2C0_DIV_CON_SHIFT = 0, 301 302 /* CRU_CLK_SEL50_CON */ 303 CLK_I2C3_PLL_SEL_SHIFT = 15, 304 CLK_I2C3_DIV_CON_SHIFT = 8, 305 CLK_I2C2_PLL_SEL_SHIFT = 7, 306 CLK_I2C2_DIV_CON_SHIFT = 0, 307 308 /* CRU_CLK_SEL52_CON */ 309 CLK_PWM_PLL_SEL_GPLL = 0, 310 CLK_PWM_PLL_SEL_24M, 311 CLK_PWM_DIV_CON_MASK = 0x7f, 312 CLK_PWM_PLL_SEL_MASK = 1, 313 CLK_PWM1_PLL_SEL_SHIFT = 15, 314 CLK_PWM1_DIV_CON_SHIFT = 8, 315 CLK_PWM0_PLL_SEL_SHIFT = 7, 316 CLK_PWM0_DIV_CON_SHIFT = 0, 317 318 /* CRU_CLK_SEL53_CON */ 319 CLK_SPI_PLL_SEL_GPLL = 0, 320 CLK_SPI_PLL_SEL_24M, 321 CLK_SPI_DIV_CON_MASK = 0x7f, 322 CLK_SPI_PLL_SEL_MASK = 1, 323 CLK_SPI1_PLL_SEL_SHIFT = 15, 324 CLK_SPI1_DIV_CON_SHIFT = 8, 325 CLK_SPI0_PLL_SEL_SHIFT = 7, 326 CLK_SPI0_DIV_CON_SHIFT = 0, 327 328 /* CRU_CLK_SEL55_CON */ 329 CLK_SARADC_DIV_CON_SHIFT = 0, 330 CLK_SARADC_DIV_CON_MASK = 0x7ff, 331 332 /* CRU_PMU_MODE */ 333 GPLL_MODE_SHIFT = 0, 334 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 335 336 /* CRU_PMU_CLK_SEL0_CON */ 337 CLK_PMU_PCLK_DIV_SHIFT = 0, 338 CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, 339 }; 340 #endif 341