1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 14 enum { 15 ROCKCHIP_SYSCON_NOC, 16 ROCKCHIP_SYSCON_GRF, 17 ROCKCHIP_SYSCON_SGRF, 18 ROCKCHIP_SYSCON_PMU, 19 }; 20 21 /* Standard Rockchip clock numbers */ 22 enum rk_clk_id { 23 CLK_OSC, 24 CLK_ARM, 25 CLK_DDR, 26 CLK_CODEC, 27 CLK_GENERAL, 28 CLK_NEW, 29 30 CLK_COUNT, 31 }; 32 33 static inline int rk_pll_id(enum rk_clk_id clk_id) 34 { 35 return clk_id - 1; 36 } 37 38 /** 39 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 40 * 41 * @return pointer to registers, or -ve error on error 42 */ 43 void *rockchip_get_cru(void); 44 45 #endif 46