1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 #define RKCLK_PLL_MODE_DEEP 2 14 15 enum { 16 ROCKCHIP_SYSCON_NOC, 17 ROCKCHIP_SYSCON_GRF, 18 ROCKCHIP_SYSCON_SGRF, 19 ROCKCHIP_SYSCON_PMU, 20 ROCKCHIP_SYSCON_PMUGRF, 21 ROCKCHIP_SYSCON_PMUSGRF, 22 ROCKCHIP_SYSCON_CIC, 23 ROCKCHIP_SYSCON_MSCH, 24 ROCKCHIP_SYSCON_USBGRF, 25 ROCKCHIP_SYSCON_PCIE30_PHY_GRF, 26 ROCKCHIP_SYSCON_PHP_GRF, 27 ROCKCHIP_SYSCON_PIPE_PHY0_GRF, 28 ROCKCHIP_SYSCON_PIPE_PHY1_GRF, 29 ROCKCHIP_SYSCON_PIPE_PHY2_GRF, 30 }; 31 32 /* Standard Rockchip clock numbers */ 33 enum rk_clk_id { 34 CLK_OSC, 35 CLK_ARM, 36 CLK_DDR, 37 CLK_CODEC, 38 CLK_GENERAL, 39 CLK_NEW, 40 41 CLK_COUNT, 42 }; 43 44 #define PLL(_type, _id, _con, _mode, _mshift, \ 45 _lshift, _pflags, _rtable) \ 46 { \ 47 .id = _id, \ 48 .type = _type, \ 49 .con_offset = _con, \ 50 .mode_offset = _mode, \ 51 .mode_shift = _mshift, \ 52 .lock_shift = _lshift, \ 53 .pll_flags = _pflags, \ 54 .rate_table = _rtable, \ 55 } 56 57 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 58 _postdiv2, _dsmpd, _frac) \ 59 { \ 60 .rate = _rate##U, \ 61 .fbdiv = _fbdiv, \ 62 .postdiv1 = _postdiv1, \ 63 .refdiv = _refdiv, \ 64 .postdiv2 = _postdiv2, \ 65 .dsmpd = _dsmpd, \ 66 .frac = _frac, \ 67 } 68 69 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 70 { \ 71 .rate = _rate##U, \ 72 .p = _p, \ 73 .m = _m, \ 74 .s = _s, \ 75 .k = _k, \ 76 } 77 78 struct rockchip_pll_rate_table { 79 unsigned long rate; 80 unsigned int nr; 81 unsigned int nf; 82 unsigned int no; 83 unsigned int nb; 84 /* for RK3036/RK3399 */ 85 unsigned int fbdiv; 86 unsigned int postdiv1; 87 unsigned int refdiv; 88 unsigned int postdiv2; 89 unsigned int dsmpd; 90 unsigned int frac; 91 /* for RK3588 */ 92 unsigned int m; 93 unsigned int p; 94 unsigned int s; 95 unsigned int k; 96 }; 97 98 enum rockchip_pll_type { 99 pll_rk3036, 100 pll_rk3066, 101 pll_rk3328, 102 pll_rk3366, 103 pll_rk3399, 104 pll_rk3588, 105 }; 106 107 struct rockchip_pll_clock { 108 unsigned int id; 109 unsigned int con_offset; 110 unsigned int mode_offset; 111 unsigned int mode_shift; 112 unsigned int lock_shift; 113 enum rockchip_pll_type type; 114 unsigned int pll_flags; 115 struct rockchip_pll_rate_table *rate_table; 116 unsigned int mode_mask; 117 }; 118 119 struct rockchip_cpu_rate_table { 120 unsigned long rate; 121 unsigned int aclk_div; 122 unsigned int pclk_div; 123 }; 124 125 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 126 void __iomem *base, ulong clk_id, 127 ulong drate); 128 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 129 void __iomem *base, ulong clk_id); 130 const struct rockchip_cpu_rate_table * 131 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 132 ulong rate); 133 134 static inline int rk_pll_id(enum rk_clk_id clk_id) 135 { 136 return clk_id - 1; 137 } 138 139 struct sysreset_reg { 140 unsigned int glb_srst_fst_value; 141 unsigned int glb_srst_snd_value; 142 }; 143 144 struct softreset_reg { 145 void __iomem *base; 146 unsigned int sf_reset_offset; 147 unsigned int sf_reset_num; 148 }; 149 150 /** 151 * clk_get_divisor() - Calculate the required clock divisior 152 * 153 * Given an input rate and a required output_rate, calculate the Rockchip 154 * divisor needed to achieve this. 155 * 156 * @input_rate: Input clock rate in Hz 157 * @output_rate: Output clock rate in Hz 158 * @return divisor register value to use 159 */ 160 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 161 { 162 uint clk_div; 163 164 clk_div = input_rate / output_rate; 165 clk_div = (clk_div + 1) & 0xfffe; 166 167 return clk_div; 168 } 169 170 /** 171 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 172 * 173 * @return pointer to registers, or -ve error on error 174 */ 175 void *rockchip_get_cru(void); 176 177 /** 178 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 179 * 180 * @return pointer to registers, or -ve error on error 181 */ 182 void *rockchip_get_pmucru(void); 183 184 struct rk3288_cru; 185 struct rk3288_grf; 186 187 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 188 189 int rockchip_get_clk(struct udevice **devp); 190 191 int rockchip_get_scmi_clk(struct udevice **devp); 192 193 #endif 194