1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 #define RKCLK_PLL_MODE_DEEP 2 14 15 enum { 16 ROCKCHIP_SYSCON_NOC, 17 ROCKCHIP_SYSCON_GRF, 18 ROCKCHIP_SYSCON_SGRF, 19 ROCKCHIP_SYSCON_PMU, 20 ROCKCHIP_SYSCON_PMUGRF, 21 ROCKCHIP_SYSCON_PMUSGRF, 22 ROCKCHIP_SYSCON_CIC, 23 ROCKCHIP_SYSCON_MSCH, 24 ROCKCHIP_SYSCON_USBGRF, 25 }; 26 27 /* Standard Rockchip clock numbers */ 28 enum rk_clk_id { 29 CLK_OSC, 30 CLK_ARM, 31 CLK_DDR, 32 CLK_CODEC, 33 CLK_GENERAL, 34 CLK_NEW, 35 36 CLK_COUNT, 37 }; 38 39 #define PLL(_type, _id, _con, _mode, _mshift, \ 40 _lshift, _pflags, _rtable) \ 41 { \ 42 .id = _id, \ 43 .type = _type, \ 44 .con_offset = _con, \ 45 .mode_offset = _mode, \ 46 .mode_shift = _mshift, \ 47 .lock_shift = _lshift, \ 48 .pll_flags = _pflags, \ 49 .rate_table = _rtable, \ 50 } 51 52 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 53 _postdiv2, _dsmpd, _frac) \ 54 { \ 55 .rate = _rate##U, \ 56 .fbdiv = _fbdiv, \ 57 .postdiv1 = _postdiv1, \ 58 .refdiv = _refdiv, \ 59 .postdiv2 = _postdiv2, \ 60 .dsmpd = _dsmpd, \ 61 .frac = _frac, \ 62 } 63 64 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 65 { \ 66 .rate = _rate##U, \ 67 .p = _p, \ 68 .m = _m, \ 69 .s = _s, \ 70 .k = _k, \ 71 } 72 73 struct rockchip_pll_rate_table { 74 unsigned long rate; 75 unsigned int nr; 76 unsigned int nf; 77 unsigned int no; 78 unsigned int nb; 79 /* for RK3036/RK3399 */ 80 unsigned int fbdiv; 81 unsigned int postdiv1; 82 unsigned int refdiv; 83 unsigned int postdiv2; 84 unsigned int dsmpd; 85 unsigned int frac; 86 /* for RK3588 */ 87 unsigned int m; 88 unsigned int p; 89 unsigned int s; 90 unsigned int k; 91 }; 92 93 enum rockchip_pll_type { 94 pll_rk3036, 95 pll_rk3066, 96 pll_rk3328, 97 pll_rk3366, 98 pll_rk3399, 99 pll_rk3588, 100 }; 101 102 struct rockchip_pll_clock { 103 unsigned int id; 104 unsigned int con_offset; 105 unsigned int mode_offset; 106 unsigned int mode_shift; 107 unsigned int lock_shift; 108 enum rockchip_pll_type type; 109 unsigned int pll_flags; 110 struct rockchip_pll_rate_table *rate_table; 111 unsigned int mode_mask; 112 }; 113 114 struct rockchip_cpu_rate_table { 115 unsigned long rate; 116 unsigned int aclk_div; 117 unsigned int pclk_div; 118 }; 119 120 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 121 void __iomem *base, ulong clk_id, 122 ulong drate); 123 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 124 void __iomem *base, ulong clk_id); 125 const struct rockchip_cpu_rate_table * 126 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 127 ulong rate); 128 129 static inline int rk_pll_id(enum rk_clk_id clk_id) 130 { 131 return clk_id - 1; 132 } 133 134 struct sysreset_reg { 135 unsigned int glb_srst_fst_value; 136 unsigned int glb_srst_snd_value; 137 }; 138 139 struct softreset_reg { 140 void __iomem *base; 141 unsigned int sf_reset_offset; 142 unsigned int sf_reset_num; 143 }; 144 145 /** 146 * clk_get_divisor() - Calculate the required clock divisior 147 * 148 * Given an input rate and a required output_rate, calculate the Rockchip 149 * divisor needed to achieve this. 150 * 151 * @input_rate: Input clock rate in Hz 152 * @output_rate: Output clock rate in Hz 153 * @return divisor register value to use 154 */ 155 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 156 { 157 uint clk_div; 158 159 clk_div = input_rate / output_rate; 160 clk_div = (clk_div + 1) & 0xfffe; 161 162 return clk_div; 163 } 164 165 /** 166 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 167 * 168 * @return pointer to registers, or -ve error on error 169 */ 170 void *rockchip_get_cru(void); 171 172 /** 173 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 174 * 175 * @return pointer to registers, or -ve error on error 176 */ 177 void *rockchip_get_pmucru(void); 178 179 struct rk3288_cru; 180 struct rk3288_grf; 181 182 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 183 184 int rockchip_get_clk(struct udevice **devp); 185 186 int rockchip_get_scmi_clk(struct udevice **devp); 187 188 #endif 189