1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 14 enum { 15 ROCKCHIP_SYSCON_NOC, 16 ROCKCHIP_SYSCON_GRF, 17 ROCKCHIP_SYSCON_SGRF, 18 ROCKCHIP_SYSCON_PMU, 19 ROCKCHIP_SYSCON_PMUGRF, 20 ROCKCHIP_SYSCON_PMUSGRF, 21 ROCKCHIP_SYSCON_CIC, 22 ROCKCHIP_SYSCON_MSCH, 23 ROCKCHIP_SYSCON_USBGRF, 24 }; 25 26 /* Standard Rockchip clock numbers */ 27 enum rk_clk_id { 28 CLK_OSC, 29 CLK_ARM, 30 CLK_DDR, 31 CLK_CODEC, 32 CLK_GENERAL, 33 CLK_NEW, 34 35 CLK_COUNT, 36 }; 37 38 static inline int rk_pll_id(enum rk_clk_id clk_id) 39 { 40 return clk_id - 1; 41 } 42 43 /** 44 * clk_get_divisor() - Calculate the required clock divisior 45 * 46 * Given an input rate and a required output_rate, calculate the Rockchip 47 * divisor needed to achieve this. 48 * 49 * @input_rate: Input clock rate in Hz 50 * @output_rate: Output clock rate in Hz 51 * @return divisor register value to use 52 */ 53 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 54 { 55 uint clk_div; 56 57 clk_div = input_rate / output_rate; 58 clk_div = (clk_div + 1) & 0xfffe; 59 60 return clk_div; 61 } 62 63 /** 64 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 65 * 66 * @return pointer to registers, or -ve error on error 67 */ 68 void *rockchip_get_cru(void); 69 70 /** 71 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 72 * 73 * @return pointer to registers, or -ve error on error 74 */ 75 void *rockchip_get_pmucru(void); 76 77 struct rk3288_cru; 78 struct rk3288_grf; 79 80 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 81 82 int rockchip_get_clk(struct udevice **devp); 83 84 #endif 85