1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 #define RKCLK_PLL_MODE_DEEP 2 14 15 enum { 16 ROCKCHIP_SYSCON_NOC, 17 ROCKCHIP_SYSCON_GRF, 18 ROCKCHIP_SYSCON_SGRF, 19 ROCKCHIP_SYSCON_PMU, 20 ROCKCHIP_SYSCON_PMUGRF, 21 ROCKCHIP_SYSCON_PMUSGRF, 22 ROCKCHIP_SYSCON_CIC, 23 ROCKCHIP_SYSCON_MSCH, 24 ROCKCHIP_SYSCON_USBGRF, 25 }; 26 27 /* Standard Rockchip clock numbers */ 28 enum rk_clk_id { 29 CLK_OSC, 30 CLK_ARM, 31 CLK_DDR, 32 CLK_CODEC, 33 CLK_GENERAL, 34 CLK_NEW, 35 36 CLK_COUNT, 37 }; 38 39 #define PLL(_type, _id, _con, _mode, _mshift, \ 40 _lshift, _pflags, _rtable) \ 41 { \ 42 .id = _id, \ 43 .type = _type, \ 44 .con_offset = _con, \ 45 .mode_offset = _mode, \ 46 .mode_shift = _mshift, \ 47 .lock_shift = _lshift, \ 48 .pll_flags = _pflags, \ 49 .rate_table = _rtable, \ 50 } 51 52 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 53 _postdiv2, _dsmpd, _frac) \ 54 { \ 55 .rate = _rate##U, \ 56 .fbdiv = _fbdiv, \ 57 .postdiv1 = _postdiv1, \ 58 .refdiv = _refdiv, \ 59 .postdiv2 = _postdiv2, \ 60 .dsmpd = _dsmpd, \ 61 .frac = _frac, \ 62 } 63 64 struct rockchip_pll_rate_table { 65 unsigned long rate; 66 unsigned int nr; 67 unsigned int nf; 68 unsigned int no; 69 unsigned int nb; 70 /* for RK3036/RK3399 */ 71 unsigned int fbdiv; 72 unsigned int postdiv1; 73 unsigned int refdiv; 74 unsigned int postdiv2; 75 unsigned int dsmpd; 76 unsigned int frac; 77 }; 78 79 enum rockchip_pll_type { 80 pll_rk3036, 81 pll_rk3066, 82 pll_rk3328, 83 pll_rk3366, 84 pll_rk3399, 85 }; 86 87 struct rockchip_pll_clock { 88 unsigned int id; 89 unsigned int con_offset; 90 unsigned int mode_offset; 91 unsigned int mode_shift; 92 unsigned int lock_shift; 93 enum rockchip_pll_type type; 94 unsigned int pll_flags; 95 struct rockchip_pll_rate_table *rate_table; 96 unsigned int mode_mask; 97 }; 98 99 struct rockchip_cpu_rate_table { 100 unsigned long rate; 101 unsigned int aclk_div; 102 unsigned int pclk_div; 103 }; 104 105 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 106 void __iomem *base, ulong clk_id, 107 ulong drate); 108 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 109 void __iomem *base, ulong clk_id); 110 const struct rockchip_cpu_rate_table * 111 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 112 ulong rate); 113 114 static inline int rk_pll_id(enum rk_clk_id clk_id) 115 { 116 return clk_id - 1; 117 } 118 119 struct sysreset_reg { 120 unsigned int glb_srst_fst_value; 121 unsigned int glb_srst_snd_value; 122 }; 123 124 struct softreset_reg { 125 void __iomem *base; 126 unsigned int sf_reset_offset; 127 unsigned int sf_reset_num; 128 }; 129 130 /** 131 * clk_get_divisor() - Calculate the required clock divisior 132 * 133 * Given an input rate and a required output_rate, calculate the Rockchip 134 * divisor needed to achieve this. 135 * 136 * @input_rate: Input clock rate in Hz 137 * @output_rate: Output clock rate in Hz 138 * @return divisor register value to use 139 */ 140 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 141 { 142 uint clk_div; 143 144 clk_div = input_rate / output_rate; 145 clk_div = (clk_div + 1) & 0xfffe; 146 147 return clk_div; 148 } 149 150 /** 151 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 152 * 153 * @return pointer to registers, or -ve error on error 154 */ 155 void *rockchip_get_cru(void); 156 157 /** 158 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 159 * 160 * @return pointer to registers, or -ve error on error 161 */ 162 void *rockchip_get_pmucru(void); 163 164 struct rk3288_cru; 165 struct rk3288_grf; 166 167 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 168 169 int rockchip_get_clk(struct udevice **devp); 170 171 int rockchip_get_scmi_clk(struct udevice **devp); 172 173 #endif 174