1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 #define RKCLK_PLL_MODE_DEEP 2 14 15 /* 16 * PLL flags 17 */ 18 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) 19 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */ 20 #define ROCKCHIP_PLL_FIXED_MODE BIT(1) 21 22 enum { 23 ROCKCHIP_SYSCON_NOC, 24 ROCKCHIP_SYSCON_GRF, 25 ROCKCHIP_SYSCON_SGRF, 26 ROCKCHIP_SYSCON_PMU, 27 ROCKCHIP_SYSCON_PMUGRF, 28 ROCKCHIP_SYSCON_PMUSGRF, 29 ROCKCHIP_SYSCON_CIC, 30 ROCKCHIP_SYSCON_MSCH, 31 ROCKCHIP_SYSCON_USBGRF, 32 ROCKCHIP_SYSCON_PCIE30_PHY_GRF, 33 ROCKCHIP_SYSCON_PHP_GRF, 34 ROCKCHIP_SYSCON_PIPE_PHY0_GRF, 35 ROCKCHIP_SYSCON_PIPE_PHY1_GRF, 36 ROCKCHIP_SYSCON_PIPE_PHY2_GRF, 37 ROCKCHIP_SYSCON_VOP_GRF, 38 ROCKCHIP_SYSCON_VO_GRF, 39 }; 40 41 /* Standard Rockchip clock numbers */ 42 enum rk_clk_id { 43 CLK_OSC, 44 CLK_ARM, 45 CLK_DDR, 46 CLK_CODEC, 47 CLK_GENERAL, 48 CLK_NEW, 49 50 CLK_COUNT, 51 }; 52 53 #define PLL(_type, _id, _con, _mode, _mshift, \ 54 _lshift, _pflags, _rtable) \ 55 { \ 56 .id = _id, \ 57 .type = _type, \ 58 .con_offset = _con, \ 59 .mode_offset = _mode, \ 60 .mode_shift = _mshift, \ 61 .lock_shift = _lshift, \ 62 .pll_flags = _pflags, \ 63 .rate_table = _rtable, \ 64 } 65 66 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 67 _postdiv2, _dsmpd, _frac) \ 68 { \ 69 .rate = _rate##U, \ 70 .fbdiv = _fbdiv, \ 71 .postdiv1 = _postdiv1, \ 72 .refdiv = _refdiv, \ 73 .postdiv2 = _postdiv2, \ 74 .dsmpd = _dsmpd, \ 75 .frac = _frac, \ 76 } 77 78 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 79 { \ 80 .rate = _rate##U, \ 81 .p = _p, \ 82 .m = _m, \ 83 .s = _s, \ 84 .k = _k, \ 85 } 86 87 struct rockchip_pll_rate_table { 88 unsigned long rate; 89 unsigned int nr; 90 unsigned int nf; 91 unsigned int no; 92 unsigned int nb; 93 /* for RK3036/RK3399 */ 94 unsigned int fbdiv; 95 unsigned int postdiv1; 96 unsigned int refdiv; 97 unsigned int postdiv2; 98 unsigned int dsmpd; 99 unsigned int frac; 100 /* for RK3588 */ 101 unsigned int m; 102 unsigned int p; 103 unsigned int s; 104 unsigned int k; 105 }; 106 107 enum rockchip_pll_type { 108 pll_rk3036, 109 pll_rk3066, 110 pll_rk3328, 111 pll_rk3366, 112 pll_rk3399, 113 pll_rk3588, 114 }; 115 116 struct rockchip_pll_clock { 117 unsigned int id; 118 unsigned int con_offset; 119 unsigned int mode_offset; 120 unsigned int mode_shift; 121 unsigned int lock_shift; 122 enum rockchip_pll_type type; 123 unsigned int pll_flags; 124 struct rockchip_pll_rate_table *rate_table; 125 unsigned int mode_mask; 126 }; 127 128 struct rockchip_cpu_rate_table { 129 unsigned long rate; 130 unsigned int aclk_div; 131 unsigned int pclk_div; 132 }; 133 134 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY 135 static inline ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 136 void __iomem *base, 137 ulong pll_id) 138 { 139 return 0; 140 } 141 142 static inline int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 143 void __iomem *base, ulong pll_id, 144 ulong drate) 145 { 146 return 0; 147 } 148 149 static inline const struct rockchip_cpu_rate_table * 150 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 151 ulong rate) 152 { 153 return NULL; 154 } 155 #else 156 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 157 void __iomem *base, ulong clk_id, 158 ulong drate); 159 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 160 void __iomem *base, ulong clk_id); 161 const struct rockchip_cpu_rate_table * 162 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 163 ulong rate); 164 #endif 165 166 static inline int rk_pll_id(enum rk_clk_id clk_id) 167 { 168 return clk_id - 1; 169 } 170 171 struct sysreset_reg { 172 unsigned int glb_srst_fst_value; 173 unsigned int glb_srst_snd_value; 174 }; 175 176 struct softreset_reg { 177 void __iomem *base; 178 unsigned int sf_reset_offset; 179 unsigned int sf_reset_num; 180 }; 181 182 /** 183 * clk_get_divisor() - Calculate the required clock divisior 184 * 185 * Given an input rate and a required output_rate, calculate the Rockchip 186 * divisor needed to achieve this. 187 * 188 * @input_rate: Input clock rate in Hz 189 * @output_rate: Output clock rate in Hz 190 * @return divisor register value to use 191 */ 192 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 193 { 194 uint clk_div; 195 196 clk_div = input_rate / output_rate; 197 clk_div = (clk_div + 1) & 0xfffe; 198 199 return clk_div; 200 } 201 202 /** 203 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 204 * 205 * @return pointer to registers, or -ve error on error 206 */ 207 void *rockchip_get_cru(void); 208 209 /** 210 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 211 * 212 * @return pointer to registers, or -ve error on error 213 */ 214 void *rockchip_get_pmucru(void); 215 216 struct rk3288_cru; 217 struct rk3288_grf; 218 219 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 220 221 int rockchip_get_clk(struct udevice **devp); 222 223 int rockchip_get_scmi_clk(struct udevice **devp); 224 225 #endif 226