1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 #define RKCLK_PLL_MODE_DEEP 2 14 15 enum { 16 ROCKCHIP_SYSCON_NOC, 17 ROCKCHIP_SYSCON_GRF, 18 ROCKCHIP_SYSCON_SGRF, 19 ROCKCHIP_SYSCON_PMU, 20 ROCKCHIP_SYSCON_PMUGRF, 21 ROCKCHIP_SYSCON_PMUSGRF, 22 ROCKCHIP_SYSCON_CIC, 23 ROCKCHIP_SYSCON_MSCH, 24 ROCKCHIP_SYSCON_USBGRF, 25 ROCKCHIP_SYSCON_PCIE30_PHY_GRF, 26 ROCKCHIP_SYSCON_PHP_GRF, 27 ROCKCHIP_SYSCON_PIPE_PHY0_GRF, 28 ROCKCHIP_SYSCON_PIPE_PHY1_GRF, 29 ROCKCHIP_SYSCON_PIPE_PHY2_GRF, 30 ROCKCHIP_SYSCON_VOP_GRF, 31 ROCKCHIP_SYSCON_VO_GRF, 32 }; 33 34 /* Standard Rockchip clock numbers */ 35 enum rk_clk_id { 36 CLK_OSC, 37 CLK_ARM, 38 CLK_DDR, 39 CLK_CODEC, 40 CLK_GENERAL, 41 CLK_NEW, 42 43 CLK_COUNT, 44 }; 45 46 #define PLL(_type, _id, _con, _mode, _mshift, \ 47 _lshift, _pflags, _rtable) \ 48 { \ 49 .id = _id, \ 50 .type = _type, \ 51 .con_offset = _con, \ 52 .mode_offset = _mode, \ 53 .mode_shift = _mshift, \ 54 .lock_shift = _lshift, \ 55 .pll_flags = _pflags, \ 56 .rate_table = _rtable, \ 57 } 58 59 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 60 _postdiv2, _dsmpd, _frac) \ 61 { \ 62 .rate = _rate##U, \ 63 .fbdiv = _fbdiv, \ 64 .postdiv1 = _postdiv1, \ 65 .refdiv = _refdiv, \ 66 .postdiv2 = _postdiv2, \ 67 .dsmpd = _dsmpd, \ 68 .frac = _frac, \ 69 } 70 71 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 72 { \ 73 .rate = _rate##U, \ 74 .p = _p, \ 75 .m = _m, \ 76 .s = _s, \ 77 .k = _k, \ 78 } 79 80 struct rockchip_pll_rate_table { 81 unsigned long rate; 82 unsigned int nr; 83 unsigned int nf; 84 unsigned int no; 85 unsigned int nb; 86 /* for RK3036/RK3399 */ 87 unsigned int fbdiv; 88 unsigned int postdiv1; 89 unsigned int refdiv; 90 unsigned int postdiv2; 91 unsigned int dsmpd; 92 unsigned int frac; 93 /* for RK3588 */ 94 unsigned int m; 95 unsigned int p; 96 unsigned int s; 97 unsigned int k; 98 }; 99 100 enum rockchip_pll_type { 101 pll_rk3036, 102 pll_rk3066, 103 pll_rk3328, 104 pll_rk3366, 105 pll_rk3399, 106 pll_rk3588, 107 }; 108 109 struct rockchip_pll_clock { 110 unsigned int id; 111 unsigned int con_offset; 112 unsigned int mode_offset; 113 unsigned int mode_shift; 114 unsigned int lock_shift; 115 enum rockchip_pll_type type; 116 unsigned int pll_flags; 117 struct rockchip_pll_rate_table *rate_table; 118 unsigned int mode_mask; 119 }; 120 121 struct rockchip_cpu_rate_table { 122 unsigned long rate; 123 unsigned int aclk_div; 124 unsigned int pclk_div; 125 }; 126 127 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY 128 static inline ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 129 void __iomem *base, 130 ulong pll_id) 131 { 132 return 0; 133 } 134 135 static inline int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 136 void __iomem *base, ulong pll_id, 137 ulong drate) 138 { 139 return 0; 140 } 141 142 static inline const struct rockchip_cpu_rate_table * 143 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 144 ulong rate) 145 { 146 return NULL; 147 } 148 #else 149 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, 150 void __iomem *base, ulong clk_id, 151 ulong drate); 152 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, 153 void __iomem *base, ulong clk_id); 154 const struct rockchip_cpu_rate_table * 155 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, 156 ulong rate); 157 #endif 158 159 static inline int rk_pll_id(enum rk_clk_id clk_id) 160 { 161 return clk_id - 1; 162 } 163 164 struct sysreset_reg { 165 unsigned int glb_srst_fst_value; 166 unsigned int glb_srst_snd_value; 167 }; 168 169 struct softreset_reg { 170 void __iomem *base; 171 unsigned int sf_reset_offset; 172 unsigned int sf_reset_num; 173 }; 174 175 /** 176 * clk_get_divisor() - Calculate the required clock divisior 177 * 178 * Given an input rate and a required output_rate, calculate the Rockchip 179 * divisor needed to achieve this. 180 * 181 * @input_rate: Input clock rate in Hz 182 * @output_rate: Output clock rate in Hz 183 * @return divisor register value to use 184 */ 185 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 186 { 187 uint clk_div; 188 189 clk_div = input_rate / output_rate; 190 clk_div = (clk_div + 1) & 0xfffe; 191 192 return clk_div; 193 } 194 195 /** 196 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 197 * 198 * @return pointer to registers, or -ve error on error 199 */ 200 void *rockchip_get_cru(void); 201 202 /** 203 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 204 * 205 * @return pointer to registers, or -ve error on error 206 */ 207 void *rockchip_get_pmucru(void); 208 209 struct rk3288_cru; 210 struct rk3288_grf; 211 212 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 213 214 int rockchip_get_clk(struct udevice **devp); 215 216 int rockchip_get_scmi_clk(struct udevice **devp); 217 218 #endif 219