126ad30e9SSimon Glass /* 226ad30e9SSimon Glass * (C) Copyright 2015 Google, Inc 326ad30e9SSimon Glass * 426ad30e9SSimon Glass * SPDX-License-Identifier: GPL-2.0 526ad30e9SSimon Glass */ 626ad30e9SSimon Glass 726ad30e9SSimon Glass #ifndef _ASM_ARCH_CLOCK_H 826ad30e9SSimon Glass #define _ASM_ARCH_CLOCK_H 926ad30e9SSimon Glass 1026ad30e9SSimon Glass /* define pll mode */ 1126ad30e9SSimon Glass #define RKCLK_PLL_MODE_SLOW 0 1226ad30e9SSimon Glass #define RKCLK_PLL_MODE_NORMAL 1 1326ad30e9SSimon Glass 1426ad30e9SSimon Glass enum { 1526ad30e9SSimon Glass ROCKCHIP_SYSCON_NOC, 1626ad30e9SSimon Glass ROCKCHIP_SYSCON_GRF, 1726ad30e9SSimon Glass ROCKCHIP_SYSCON_SGRF, 1826ad30e9SSimon Glass ROCKCHIP_SYSCON_PMU, 19c55e30ebSKever Yang ROCKCHIP_SYSCON_PMUGRF, 2026ad30e9SSimon Glass }; 2126ad30e9SSimon Glass 2226ad30e9SSimon Glass /* Standard Rockchip clock numbers */ 2326ad30e9SSimon Glass enum rk_clk_id { 2426ad30e9SSimon Glass CLK_OSC, 2526ad30e9SSimon Glass CLK_ARM, 2626ad30e9SSimon Glass CLK_DDR, 2726ad30e9SSimon Glass CLK_CODEC, 2826ad30e9SSimon Glass CLK_GENERAL, 2926ad30e9SSimon Glass CLK_NEW, 3026ad30e9SSimon Glass 3126ad30e9SSimon Glass CLK_COUNT, 3226ad30e9SSimon Glass }; 3326ad30e9SSimon Glass 3426ad30e9SSimon Glass static inline int rk_pll_id(enum rk_clk_id clk_id) 3526ad30e9SSimon Glass { 3626ad30e9SSimon Glass return clk_id - 1; 3726ad30e9SSimon Glass } 3826ad30e9SSimon Glass 3926ad30e9SSimon Glass /** 401b2fd5bfSSimon Glass * clk_get_divisor() - Calculate the required clock divisior 411b2fd5bfSSimon Glass * 421b2fd5bfSSimon Glass * Given an input rate and a required output_rate, calculate the Rockchip 431b2fd5bfSSimon Glass * divisor needed to achieve this. 441b2fd5bfSSimon Glass * 451b2fd5bfSSimon Glass * @input_rate: Input clock rate in Hz 461b2fd5bfSSimon Glass * @output_rate: Output clock rate in Hz 471b2fd5bfSSimon Glass * @return divisor register value to use 481b2fd5bfSSimon Glass */ 491b2fd5bfSSimon Glass static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 501b2fd5bfSSimon Glass { 511b2fd5bfSSimon Glass uint clk_div; 521b2fd5bfSSimon Glass 531b2fd5bfSSimon Glass clk_div = input_rate / output_rate; 541b2fd5bfSSimon Glass clk_div = (clk_div + 1) & 0xfffe; 551b2fd5bfSSimon Glass 561b2fd5bfSSimon Glass return clk_div; 571b2fd5bfSSimon Glass } 581b2fd5bfSSimon Glass 591b2fd5bfSSimon Glass /** 6026ad30e9SSimon Glass * rockchip_get_cru() - get a pointer to the clock/reset unit registers 6126ad30e9SSimon Glass * 6226ad30e9SSimon Glass * @return pointer to registers, or -ve error on error 6326ad30e9SSimon Glass */ 6426ad30e9SSimon Glass void *rockchip_get_cru(void); 6526ad30e9SSimon Glass 66*5ae2fd97SKever Yang /** 67*5ae2fd97SKever Yang * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 68*5ae2fd97SKever Yang * 69*5ae2fd97SKever Yang * @return pointer to registers, or -ve error on error 70*5ae2fd97SKever Yang */ 71*5ae2fd97SKever Yang void *rockchip_get_pmucru(void); 72*5ae2fd97SKever Yang 73dae594f2SSimon Glass struct rk3288_cru; 74dae594f2SSimon Glass struct rk3288_grf; 75dae594f2SSimon Glass 76b339b5dbSHeiko Stübner void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 77dae594f2SSimon Glass 78a617c5d3SSimon Glass int rockchip_get_clk(struct udevice **devp); 79a617c5d3SSimon Glass 8026ad30e9SSimon Glass #endif 81