126ad30e9SSimon Glass /* 226ad30e9SSimon Glass * (C) Copyright 2015 Google, Inc 326ad30e9SSimon Glass * 426ad30e9SSimon Glass * SPDX-License-Identifier: GPL-2.0 526ad30e9SSimon Glass */ 626ad30e9SSimon Glass 726ad30e9SSimon Glass #ifndef _ASM_ARCH_CLOCK_H 826ad30e9SSimon Glass #define _ASM_ARCH_CLOCK_H 926ad30e9SSimon Glass 1026ad30e9SSimon Glass /* define pll mode */ 1126ad30e9SSimon Glass #define RKCLK_PLL_MODE_SLOW 0 1226ad30e9SSimon Glass #define RKCLK_PLL_MODE_NORMAL 1 1326ad30e9SSimon Glass 1426ad30e9SSimon Glass enum { 1526ad30e9SSimon Glass ROCKCHIP_SYSCON_NOC, 1626ad30e9SSimon Glass ROCKCHIP_SYSCON_GRF, 1726ad30e9SSimon Glass ROCKCHIP_SYSCON_SGRF, 1826ad30e9SSimon Glass ROCKCHIP_SYSCON_PMU, 1926ad30e9SSimon Glass }; 2026ad30e9SSimon Glass 2126ad30e9SSimon Glass /* Standard Rockchip clock numbers */ 2226ad30e9SSimon Glass enum rk_clk_id { 2326ad30e9SSimon Glass CLK_OSC, 2426ad30e9SSimon Glass CLK_ARM, 2526ad30e9SSimon Glass CLK_DDR, 2626ad30e9SSimon Glass CLK_CODEC, 2726ad30e9SSimon Glass CLK_GENERAL, 2826ad30e9SSimon Glass CLK_NEW, 2926ad30e9SSimon Glass 3026ad30e9SSimon Glass CLK_COUNT, 3126ad30e9SSimon Glass }; 3226ad30e9SSimon Glass 3326ad30e9SSimon Glass static inline int rk_pll_id(enum rk_clk_id clk_id) 3426ad30e9SSimon Glass { 3526ad30e9SSimon Glass return clk_id - 1; 3626ad30e9SSimon Glass } 3726ad30e9SSimon Glass 3826ad30e9SSimon Glass /** 39*1b2fd5bfSSimon Glass * clk_get_divisor() - Calculate the required clock divisior 40*1b2fd5bfSSimon Glass * 41*1b2fd5bfSSimon Glass * Given an input rate and a required output_rate, calculate the Rockchip 42*1b2fd5bfSSimon Glass * divisor needed to achieve this. 43*1b2fd5bfSSimon Glass * 44*1b2fd5bfSSimon Glass * @input_rate: Input clock rate in Hz 45*1b2fd5bfSSimon Glass * @output_rate: Output clock rate in Hz 46*1b2fd5bfSSimon Glass * @return divisor register value to use 47*1b2fd5bfSSimon Glass */ 48*1b2fd5bfSSimon Glass static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 49*1b2fd5bfSSimon Glass { 50*1b2fd5bfSSimon Glass uint clk_div; 51*1b2fd5bfSSimon Glass 52*1b2fd5bfSSimon Glass clk_div = input_rate / output_rate; 53*1b2fd5bfSSimon Glass clk_div = (clk_div + 1) & 0xfffe; 54*1b2fd5bfSSimon Glass 55*1b2fd5bfSSimon Glass return clk_div; 56*1b2fd5bfSSimon Glass } 57*1b2fd5bfSSimon Glass 58*1b2fd5bfSSimon Glass /** 5926ad30e9SSimon Glass * rockchip_get_cru() - get a pointer to the clock/reset unit registers 6026ad30e9SSimon Glass * 6126ad30e9SSimon Glass * @return pointer to registers, or -ve error on error 6226ad30e9SSimon Glass */ 6326ad30e9SSimon Glass void *rockchip_get_cru(void); 6426ad30e9SSimon Glass 6526ad30e9SSimon Glass #endif 66