1*980db8caSSylvain Lemieux /* 2*980db8caSSylvain Lemieux * LPC32xx DMA Controller Interface 3*980db8caSSylvain Lemieux * 4*980db8caSSylvain Lemieux * Copyright (C) 2008 by NXP Semiconductors 5*980db8caSSylvain Lemieux * @Author: Kevin Wells 6*980db8caSSylvain Lemieux * @Descr: Definitions for LPC3250 chip 7*980db8caSSylvain Lemieux * @References: NXP LPC3250 User's Guide 8*980db8caSSylvain Lemieux * 9*980db8caSSylvain Lemieux * SPDX-License-Identifier: GPL-2.0+ 10*980db8caSSylvain Lemieux */ 11*980db8caSSylvain Lemieux 12*980db8caSSylvain Lemieux #ifndef _LPC32XX_DMA_H 13*980db8caSSylvain Lemieux #define _LPC32XX_DMA_H 14*980db8caSSylvain Lemieux 15*980db8caSSylvain Lemieux #include <common.h> 16*980db8caSSylvain Lemieux 17*980db8caSSylvain Lemieux /* 18*980db8caSSylvain Lemieux * DMA linked list structure used with a channel's LLI register; 19*980db8caSSylvain Lemieux * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 20*980db8caSSylvain Lemieux * tables 84, 85, 86 & 87 for details. 21*980db8caSSylvain Lemieux */ 22*980db8caSSylvain Lemieux struct lpc32xx_dmac_ll { 23*980db8caSSylvain Lemieux u32 dma_src; 24*980db8caSSylvain Lemieux u32 dma_dest; 25*980db8caSSylvain Lemieux u32 next_lli; 26*980db8caSSylvain Lemieux u32 next_ctrl; 27*980db8caSSylvain Lemieux }; 28*980db8caSSylvain Lemieux 29*980db8caSSylvain Lemieux /* control register definitions */ 30*980db8caSSylvain Lemieux #define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */ 31*980db8caSSylvain Lemieux #define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */ 32*980db8caSSylvain Lemieux #define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */ 33*980db8caSSylvain Lemieux #define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */ 34*980db8caSSylvain Lemieux #define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */ 35*980db8caSSylvain Lemieux #define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */ 36*980db8caSSylvain Lemieux #define DMAC_CHAN_DEST_BURST_1 0 37*980db8caSSylvain Lemieux #define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */ 38*980db8caSSylvain Lemieux #define DMAC_CHAN_SRC_BURST_1 0 39*980db8caSSylvain Lemieux #define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */ 40*980db8caSSylvain Lemieux 41*980db8caSSylvain Lemieux /* 42*980db8caSSylvain Lemieux * config_ch register definitions 43*980db8caSSylvain Lemieux * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller 44*980db8caSSylvain Lemieux * DMAC_DEST_PERIP: Macro for loading destination peripheral 45*980db8caSSylvain Lemieux * DMAC_SRC_PERIP: Macro for loading source peripheral 46*980db8caSSylvain Lemieux */ 47*980db8caSSylvain Lemieux #define DMAC_CHAN_FLOW_D_M2P (0x1 << 11) 48*980db8caSSylvain Lemieux #define DMAC_CHAN_FLOW_D_P2M (0x2 << 11) 49*980db8caSSylvain Lemieux #define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6) 50*980db8caSSylvain Lemieux #define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1) 51*980db8caSSylvain Lemieux 52*980db8caSSylvain Lemieux /* 53*980db8caSSylvain Lemieux * config_ch register definitions 54*980db8caSSylvain Lemieux * (source and destination peripheral ID numbers). 55*980db8caSSylvain Lemieux * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros. 56*980db8caSSylvain Lemieux */ 57*980db8caSSylvain Lemieux #define DMA_PERID_NAND1 1 58*980db8caSSylvain Lemieux 59*980db8caSSylvain Lemieux /* Channel enable bit */ 60*980db8caSSylvain Lemieux #define DMAC_CHAN_ENABLE (1 << 0) 61*980db8caSSylvain Lemieux 62*980db8caSSylvain Lemieux int lpc32xx_dma_get_channel(void); 63*980db8caSSylvain Lemieux int lpc32xx_dma_start_xfer(unsigned int channel, 64*980db8caSSylvain Lemieux const struct lpc32xx_dmac_ll *desc, u32 config); 65*980db8caSSylvain Lemieux int lpc32xx_dma_wait_status(unsigned int channel); 66*980db8caSSylvain Lemieux 67*980db8caSSylvain Lemieux #endif /* _LPC32XX_DMA_H */ 68