1/* 2 * dts file for Xilinx ZynqMP 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10/ { 11 compatible = "xlnx,zynqmp"; 12 #address-cells = <2>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 compatible = "arm,cortex-a53", "arm,armv8"; 21 device_type = "cpu"; 22 enable-method = "psci"; 23 reg = <0x0>; 24 }; 25 26 cpu@1 { 27 compatible = "arm,cortex-a53", "arm,armv8"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 reg = <0x1>; 31 }; 32 33 cpu@2 { 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x2>; 38 }; 39 40 cpu@3 { 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x3>; 45 }; 46 }; 47 48 power-domains { 49 compatible = "xlnx,zynqmp-genpd"; 50 51 pd_usb0: pd-usb0 { 52 #power-domain-cells = <0x0>; 53 pd-id = <0x16>; 54 }; 55 56 pd_usb1: pd-usb1 { 57 #power-domain-cells = <0x0>; 58 pd-id = <0x17>; 59 }; 60 61 pd_sata: pd-sata { 62 #power-domain-cells = <0x0>; 63 pd-id = <0x1c>; 64 }; 65 66 pd_spi0: pd-spi0 { 67 #power-domain-cells = <0x0>; 68 pd-id = <0x23>; 69 }; 70 71 pd_spi1: pd-spi1 { 72 #power-domain-cells = <0x0>; 73 pd-id = <0x24>; 74 }; 75 76 pd_uart0: pd-uart0 { 77 #power-domain-cells = <0x0>; 78 pd-id = <0x21>; 79 }; 80 81 pd_uart1: pd-uart1 { 82 #power-domain-cells = <0x0>; 83 pd-id = <0x22>; 84 }; 85 86 pd_eth0: pd-eth0 { 87 #power-domain-cells = <0x0>; 88 pd-id = <0x1d>; 89 }; 90 91 pd_eth1: pd-eth1 { 92 #power-domain-cells = <0x0>; 93 pd-id = <0x1e>; 94 }; 95 96 pd_eth2: pd-eth2 { 97 #power-domain-cells = <0x0>; 98 pd-id = <0x1f>; 99 }; 100 101 pd_eth3: pd-eth3 { 102 #power-domain-cells = <0x0>; 103 pd-id = <0x20>; 104 }; 105 106 pd_i2c0: pd-i2c0 { 107 #power-domain-cells = <0x0>; 108 pd-id = <0x25>; 109 }; 110 111 pd_i2c1: pd-i2c1 { 112 #power-domain-cells = <0x0>; 113 pd-id = <0x26>; 114 }; 115 116 pd_dp: pd-dp { 117 /* fixme: what to attach to */ 118 #power-domain-cells = <0x0>; 119 pd-id = <0x29>; 120 }; 121 122 pd_gdma: pd-gdma { 123 #power-domain-cells = <0x0>; 124 pd-id = <0x2a>; 125 }; 126 127 pd_adma: pd-adma { 128 #power-domain-cells = <0x0>; 129 pd-id = <0x2b>; 130 }; 131 132 pd_ttc0: pd-ttc0 { 133 #power-domain-cells = <0x0>; 134 pd-id = <0x18>; 135 }; 136 137 pd_ttc1: pd-ttc1 { 138 #power-domain-cells = <0x0>; 139 pd-id = <0x19>; 140 }; 141 142 pd_ttc2: pd-ttc2 { 143 #power-domain-cells = <0x0>; 144 pd-id = <0x1a>; 145 }; 146 147 pd_ttc3: pd-ttc3 { 148 #power-domain-cells = <0x0>; 149 pd-id = <0x1b>; 150 }; 151 152 pd_sd0: pd-sd0 { 153 #power-domain-cells = <0x0>; 154 pd-id = <0x27>; 155 }; 156 157 pd_sd1: pd-sd1 { 158 #power-domain-cells = <0x0>; 159 pd-id = <0x28>; 160 }; 161 162 pd_nand: pd-nand { 163 #power-domain-cells = <0x0>; 164 pd-id = <0x2c>; 165 }; 166 167 pd_qspi: pd-qspi { 168 #power-domain-cells = <0x0>; 169 pd-id = <0x2d>; 170 }; 171 172 pd_gpio: pd-gpio { 173 #power-domain-cells = <0x0>; 174 pd-id = <0x2e>; 175 }; 176 177 pd_can0: pd-can0 { 178 #power-domain-cells = <0x0>; 179 pd-id = <0x2f>; 180 }; 181 182 pd_can1: pd-can1 { 183 #power-domain-cells = <0x0>; 184 pd-id = <0x30>; 185 }; 186 187 pd_ddr: pd-ddr { 188 #power-domain-cells = <0x0>; 189 pd-id = <0x37>; 190 }; 191 192 pd_apll: pd-apll { 193 #power-domain-cells = <0x0>; 194 pd-id = <0x32>; 195 }; 196 197 pd_vpll: pd-vpll { 198 #power-domain-cells = <0x0>; 199 pd-id = <0x33>; 200 }; 201 202 pd_dpll: pd-dpll { 203 #power-domain-cells = <0x0>; 204 pd-id = <0x34>; 205 }; 206 207 pd_rpll: pd-rpll { 208 #power-domain-cells = <0x0>; 209 pd-id = <0x35>; 210 }; 211 212 pd_iopll: pd-iopll { 213 #power-domain-cells = <0x0>; 214 pd-id = <0x36>; 215 }; 216 }; 217 218 pmu { 219 compatible = "arm,armv8-pmuv3"; 220 interrupt-parent = <&gic>; 221 interrupts = <0 143 4>, 222 <0 144 4>, 223 <0 145 4>, 224 <0 146 4>; 225 }; 226 227 psci { 228 compatible = "arm,psci-0.2"; 229 method = "smc"; 230 }; 231 232 firmware { 233 compatible = "xlnx,zynqmp-pm"; 234 method = "smc"; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupt-parent = <&gic>; 240 interrupts = <1 13 0xf01>, 241 <1 14 0xf01>, 242 <1 11 0xf01>, 243 <1 10 0xf01>; 244 }; 245 246 amba_apu: amba_apu { 247 compatible = "simple-bus"; 248 #address-cells = <2>; 249 #size-cells = <1>; 250 ranges; 251 252 gic: interrupt-controller@f9010000 { 253 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 254 #interrupt-cells = <3>; 255 reg = <0x0 0xf9010000 0x10000>, 256 <0x0 0xf902f000 0x2000>, 257 <0x0 0xf9040000 0x20000>, 258 <0x0 0xf906f000 0x2000>; 259 interrupt-controller; 260 interrupt-parent = <&gic>; 261 interrupts = <1 9 0xf04>; 262 }; 263 }; 264 265 amba: amba { 266 compatible = "simple-bus"; 267 #address-cells = <2>; 268 #size-cells = <1>; 269 ranges; 270 271 can0: can@ff060000 { 272 compatible = "xlnx,zynq-can-1.0"; 273 status = "disabled"; 274 clock-names = "can_clk", "pclk"; 275 reg = <0x0 0xff060000 0x1000>; 276 interrupts = <0 23 4>; 277 interrupt-parent = <&gic>; 278 tx-fifo-depth = <0x40>; 279 rx-fifo-depth = <0x40>; 280 power-domains = <&pd_can0>; 281 }; 282 283 can1: can@ff070000 { 284 compatible = "xlnx,zynq-can-1.0"; 285 status = "disabled"; 286 clock-names = "can_clk", "pclk"; 287 reg = <0x0 0xff070000 0x1000>; 288 interrupts = <0 24 4>; 289 interrupt-parent = <&gic>; 290 tx-fifo-depth = <0x40>; 291 rx-fifo-depth = <0x40>; 292 power-domains = <&pd_can1>; 293 }; 294 295 /* GDMA */ 296 fpd_dma_chan1: dma@fd500000 { 297 status = "disabled"; 298 compatible = "xlnx,zynqmp-dma-1.0"; 299 reg = <0x0 0xfd500000 0x1000>; 300 interrupt-parent = <&gic>; 301 interrupts = <0 124 4>; 302 xlnx,id = <0>; 303 xlnx,bus-width = <128>; 304 power-domains = <&pd_gdma>; 305 }; 306 307 fpd_dma_chan2: dma@fd510000 { 308 status = "disabled"; 309 compatible = "xlnx,zynqmp-dma-1.0"; 310 reg = <0x0 0xfd510000 0x1000>; 311 interrupt-parent = <&gic>; 312 interrupts = <0 125 4>; 313 xlnx,id = <1>; 314 xlnx,bus-width = <128>; 315 power-domains = <&pd_gdma>; 316 }; 317 318 fpd_dma_chan3: dma@fd520000 { 319 status = "disabled"; 320 compatible = "xlnx,zynqmp-dma-1.0"; 321 reg = <0x0 0xfd520000 0x1000>; 322 interrupt-parent = <&gic>; 323 interrupts = <0 126 4>; 324 xlnx,id = <2>; 325 xlnx,bus-width = <128>; 326 power-domains = <&pd_gdma>; 327 }; 328 329 fpd_dma_chan4: dma@fd530000 { 330 status = "disabled"; 331 compatible = "xlnx,zynqmp-dma-1.0"; 332 reg = <0x0 0xfd530000 0x1000>; 333 interrupt-parent = <&gic>; 334 interrupts = <0 127 4>; 335 xlnx,id = <3>; 336 xlnx,bus-width = <128>; 337 power-domains = <&pd_gdma>; 338 }; 339 340 fpd_dma_chan5: dma@fd540000 { 341 status = "disabled"; 342 compatible = "xlnx,zynqmp-dma-1.0"; 343 reg = <0x0 0xfd540000 0x1000>; 344 interrupt-parent = <&gic>; 345 interrupts = <0 128 4>; 346 xlnx,id = <4>; 347 xlnx,bus-width = <128>; 348 power-domains = <&pd_gdma>; 349 }; 350 351 fpd_dma_chan6: dma@fd550000 { 352 status = "disabled"; 353 compatible = "xlnx,zynqmp-dma-1.0"; 354 reg = <0x0 0xfd550000 0x1000>; 355 interrupt-parent = <&gic>; 356 interrupts = <0 129 4>; 357 xlnx,id = <5>; 358 xlnx,bus-width = <128>; 359 power-domains = <&pd_gdma>; 360 }; 361 362 fpd_dma_chan7: dma@fd560000 { 363 status = "disabled"; 364 compatible = "xlnx,zynqmp-dma-1.0"; 365 reg = <0x0 0xfd560000 0x1000>; 366 interrupt-parent = <&gic>; 367 interrupts = <0 130 4>; 368 xlnx,id = <6>; 369 xlnx,bus-width = <128>; 370 power-domains = <&pd_gdma>; 371 }; 372 373 fpd_dma_chan8: dma@fd570000 { 374 status = "disabled"; 375 compatible = "xlnx,zynqmp-dma-1.0"; 376 reg = <0x0 0xfd570000 0x1000>; 377 interrupt-parent = <&gic>; 378 interrupts = <0 131 4>; 379 xlnx,id = <7>; 380 xlnx,bus-width = <128>; 381 power-domains = <&pd_gdma>; 382 }; 383 384 gpu: gpu@fd4b0000 { 385 status = "disabled"; 386 compatible = "arm,mali-400", "arm,mali-utgard"; 387 reg = <0x0 0xfd4b0000 0x30000>; 388 interrupt-parent = <&gic>; 389 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 390 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 391 }; 392 393 /* ADMA */ 394 lpd_dma_chan1: dma@ffa80000 { 395 status = "disabled"; 396 compatible = "xlnx,zynqmp-dma-1.0"; 397 reg = <0x0 0xffa80000 0x1000>; 398 interrupt-parent = <&gic>; 399 interrupts = <0 77 4>; 400 xlnx,id = <0>; 401 xlnx,bus-width = <64>; 402 power-domains = <&pd_adma>; 403 }; 404 405 lpd_dma_chan2: dma@ffa90000 { 406 status = "disabled"; 407 compatible = "xlnx,zynqmp-dma-1.0"; 408 reg = <0x0 0xffa90000 0x1000>; 409 interrupt-parent = <&gic>; 410 interrupts = <0 78 4>; 411 xlnx,id = <1>; 412 xlnx,bus-width = <64>; 413 power-domains = <&pd_adma>; 414 }; 415 416 lpd_dma_chan3: dma@ffaa0000 { 417 status = "disabled"; 418 compatible = "xlnx,zynqmp-dma-1.0"; 419 reg = <0x0 0xffaa0000 0x1000>; 420 interrupt-parent = <&gic>; 421 interrupts = <0 79 4>; 422 xlnx,id = <2>; 423 xlnx,bus-width = <64>; 424 power-domains = <&pd_adma>; 425 }; 426 427 lpd_dma_chan4: dma@ffab0000 { 428 status = "disabled"; 429 compatible = "xlnx,zynqmp-dma-1.0"; 430 reg = <0x0 0xffab0000 0x1000>; 431 interrupt-parent = <&gic>; 432 interrupts = <0 80 4>; 433 xlnx,id = <3>; 434 xlnx,bus-width = <64>; 435 power-domains = <&pd_adma>; 436 }; 437 438 lpd_dma_chan5: dma@ffac0000 { 439 status = "disabled"; 440 compatible = "xlnx,zynqmp-dma-1.0"; 441 reg = <0x0 0xffac0000 0x1000>; 442 interrupt-parent = <&gic>; 443 interrupts = <0 81 4>; 444 xlnx,id = <4>; 445 xlnx,bus-width = <64>; 446 power-domains = <&pd_adma>; 447 }; 448 449 lpd_dma_chan6: dma@ffad0000 { 450 status = "disabled"; 451 compatible = "xlnx,zynqmp-dma-1.0"; 452 reg = <0x0 0xffad0000 0x1000>; 453 interrupt-parent = <&gic>; 454 interrupts = <0 82 4>; 455 xlnx,id = <5>; 456 xlnx,bus-width = <64>; 457 power-domains = <&pd_adma>; 458 }; 459 460 lpd_dma_chan7: dma@ffae0000 { 461 status = "disabled"; 462 compatible = "xlnx,zynqmp-dma-1.0"; 463 reg = <0x0 0xffae0000 0x1000>; 464 interrupt-parent = <&gic>; 465 interrupts = <0 83 4>; 466 xlnx,id = <6>; 467 xlnx,bus-width = <64>; 468 power-domains = <&pd_adma>; 469 }; 470 471 lpd_dma_chan8: dma@ffaf0000 { 472 status = "disabled"; 473 compatible = "xlnx,zynqmp-dma-1.0"; 474 reg = <0x0 0xffaf0000 0x1000>; 475 interrupt-parent = <&gic>; 476 interrupts = <0 84 4>; 477 xlnx,id = <7>; 478 xlnx,bus-width = <64>; 479 power-domains = <&pd_adma>; 480 }; 481 482 nand0: nand@ff100000 { 483 compatible = "arasan,nfc-v3p10"; 484 status = "disabled"; 485 reg = <0x0 0xff100000 0x1000>; 486 clock-names = "clk_sys", "clk_flash"; 487 interrupt-parent = <&gic>; 488 interrupts = <0 14 4>; 489 #address-cells = <2>; 490 #size-cells = <1>; 491 power-domains = <&pd_nand>; 492 }; 493 494 gem0: ethernet@ff0b0000 { 495 compatible = "cdns,zynqmp-gem"; 496 status = "disabled"; 497 interrupt-parent = <&gic>; 498 interrupts = <0 57 4>, <0 57 4>; 499 reg = <0x0 0xff0b0000 0x1000>; 500 clock-names = "pclk", "hclk", "tx_clk"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 #stream-id-cells = <1>; 504 power-domains = <&pd_eth0>; 505 }; 506 507 gem1: ethernet@ff0c0000 { 508 compatible = "cdns,zynqmp-gem"; 509 status = "disabled"; 510 interrupt-parent = <&gic>; 511 interrupts = <0 59 4>, <0 59 4>; 512 reg = <0x0 0xff0c0000 0x1000>; 513 clock-names = "pclk", "hclk", "tx_clk"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 #stream-id-cells = <1>; 517 power-domains = <&pd_eth1>; 518 }; 519 520 gem2: ethernet@ff0d0000 { 521 compatible = "cdns,zynqmp-gem"; 522 status = "disabled"; 523 interrupt-parent = <&gic>; 524 interrupts = <0 61 4>, <0 61 4>; 525 reg = <0x0 0xff0d0000 0x1000>; 526 clock-names = "pclk", "hclk", "tx_clk"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 #stream-id-cells = <1>; 530 power-domains = <&pd_eth2>; 531 }; 532 533 gem3: ethernet@ff0e0000 { 534 compatible = "cdns,zynqmp-gem"; 535 status = "disabled"; 536 interrupt-parent = <&gic>; 537 interrupts = <0 63 4>, <0 63 4>; 538 reg = <0x0 0xff0e0000 0x1000>; 539 clock-names = "pclk", "hclk", "tx_clk"; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 #stream-id-cells = <1>; 543 power-domains = <&pd_eth3>; 544 }; 545 546 gpio: gpio@ff0a0000 { 547 compatible = "xlnx,zynqmp-gpio-1.0"; 548 status = "disabled"; 549 #gpio-cells = <0x2>; 550 interrupt-parent = <&gic>; 551 interrupts = <0 16 4>; 552 reg = <0x0 0xff0a0000 0x1000>; 553 power-domains = <&pd_gpio>; 554 }; 555 556 i2c0: i2c@ff020000 { 557 compatible = "cdns,i2c-r1p10"; 558 status = "disabled"; 559 interrupt-parent = <&gic>; 560 interrupts = <0 17 4>; 561 reg = <0x0 0xff020000 0x1000>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 power-domains = <&pd_i2c0>; 565 }; 566 567 i2c1: i2c@ff030000 { 568 compatible = "cdns,i2c-r1p10"; 569 status = "disabled"; 570 interrupt-parent = <&gic>; 571 interrupts = <0 18 4>; 572 reg = <0x0 0xff030000 0x1000>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 power-domains = <&pd_i2c1>; 576 }; 577 578 pcie: pcie@fd0e0000 { 579 compatible = "xlnx,nwl-pcie-2.11"; 580 status = "disabled"; 581 #address-cells = <3>; 582 #size-cells = <2>; 583 #interrupt-cells = <1>; 584 device_type = "pci"; 585 interrupt-parent = <&gic>; 586 interrupts = < 0 118 4>, 587 < 0 116 4>, 588 < 0 115 4>, /* MSI_1 [63...32] */ 589 < 0 114 4 >; /* MSI_0 [31...0] */ 590 interrupt-names = "misc", "intx", "msi_1", "msi_0"; 591 reg = <0x0 0xfd0e0000 0x1000>, 592 <0x0 0xfd480000 0x1000>, 593 <0x0 0xe0000000 0x1000000>; 594 reg-names = "breg", "pcireg", "cfg"; 595 ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; 596 }; 597 598 qspi: spi@ff0f0000 { 599 compatible = "xlnx,zynqmp-qspi-1.0"; 600 status = "disabled"; 601 clock-names = "ref_clk", "pclk"; 602 interrupts = <0 15 4>; 603 interrupt-parent = <&gic>; 604 num-cs = <1>; 605 reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 power-domains = <&pd_qspi>; 609 }; 610 611 rtc: rtc@ffa60000 { 612 compatible = "xlnx,zynqmp-rtc"; 613 status = "disabled"; 614 reg = <0x0 0xffa60000 0x100>; 615 interrupt-parent = <&gic>; 616 interrupts = <0 26 4>, <0 27 4>; 617 interrupt-names = "alarm", "sec"; 618 }; 619 620 sata: ahci@fd0c0000 { 621 compatible = "ceva,ahci-1v84"; 622 status = "disabled"; 623 reg = <0x0 0xfd0c0000 0x2000>; 624 interrupt-parent = <&gic>; 625 interrupts = <0 133 4>; 626 power-domains = <&pd_sata>; 627 }; 628 629 sdhci0: sdhci@ff160000 { 630 compatible = "arasan,sdhci-8.9a"; 631 status = "disabled"; 632 interrupt-parent = <&gic>; 633 interrupts = <0 48 4>; 634 reg = <0x0 0xff160000 0x1000>; 635 clock-names = "clk_xin", "clk_ahb"; 636 broken-tuning; 637 power-domains = <&pd_sd0>; 638 }; 639 640 sdhci1: sdhci@ff170000 { 641 compatible = "arasan,sdhci-8.9a"; 642 status = "disabled"; 643 interrupt-parent = <&gic>; 644 interrupts = <0 49 4>; 645 reg = <0x0 0xff170000 0x1000>; 646 clock-names = "clk_xin", "clk_ahb"; 647 broken-tuning; 648 power-domains = <&pd_sd1>; 649 }; 650 651 smmu: smmu@fd800000 { 652 compatible = "arm,mmu-500"; 653 reg = <0x0 0xfd800000 0x20000>; 654 #global-interrupts = <1>; 655 interrupt-parent = <&gic>; 656 interrupts = <0 155 4>, 657 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 658 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 659 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 660 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 661 mmu-masters = < &gem0 0x874 662 &gem1 0x875 663 &gem2 0x876 664 &gem3 0x877 >; 665 }; 666 667 spi0: spi@ff040000 { 668 compatible = "cdns,spi-r1p6"; 669 status = "disabled"; 670 interrupt-parent = <&gic>; 671 interrupts = <0 19 4>; 672 reg = <0x0 0xff040000 0x1000>; 673 clock-names = "ref_clk", "pclk"; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 power-domains = <&pd_spi0>; 677 }; 678 679 spi1: spi@ff050000 { 680 compatible = "cdns,spi-r1p6"; 681 status = "disabled"; 682 interrupt-parent = <&gic>; 683 interrupts = <0 20 4>; 684 reg = <0x0 0xff050000 0x1000>; 685 clock-names = "ref_clk", "pclk"; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 power-domains = <&pd_spi1>; 689 }; 690 691 ttc0: timer@ff110000 { 692 compatible = "cdns,ttc"; 693 status = "disabled"; 694 interrupt-parent = <&gic>; 695 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 696 reg = <0x0 0xff110000 0x1000>; 697 timer-width = <32>; 698 power-domains = <&pd_ttc0>; 699 }; 700 701 ttc1: timer@ff120000 { 702 compatible = "cdns,ttc"; 703 status = "disabled"; 704 interrupt-parent = <&gic>; 705 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 706 reg = <0x0 0xff120000 0x1000>; 707 timer-width = <32>; 708 power-domains = <&pd_ttc1>; 709 }; 710 711 ttc2: timer@ff130000 { 712 compatible = "cdns,ttc"; 713 status = "disabled"; 714 interrupt-parent = <&gic>; 715 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 716 reg = <0x0 0xff130000 0x1000>; 717 timer-width = <32>; 718 power-domains = <&pd_ttc2>; 719 }; 720 721 ttc3: timer@ff140000 { 722 compatible = "cdns,ttc"; 723 status = "disabled"; 724 interrupt-parent = <&gic>; 725 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 726 reg = <0x0 0xff140000 0x1000>; 727 timer-width = <32>; 728 power-domains = <&pd_ttc3>; 729 }; 730 731 uart0: serial@ff000000 { 732 compatible = "cdns,uart-r1p12"; 733 status = "disabled"; 734 interrupt-parent = <&gic>; 735 interrupts = <0 21 4>; 736 reg = <0x0 0xff000000 0x1000>; 737 clock-names = "uart_clk", "pclk"; 738 power-domains = <&pd_uart0>; 739 }; 740 741 uart1: serial@ff010000 { 742 compatible = "cdns,uart-r1p12"; 743 status = "disabled"; 744 interrupt-parent = <&gic>; 745 interrupts = <0 22 4>; 746 reg = <0x0 0xff010000 0x1000>; 747 clock-names = "uart_clk", "pclk"; 748 power-domains = <&pd_uart1>; 749 }; 750 751 usb0: usb@fe200000 { 752 compatible = "snps,dwc3"; 753 status = "disabled"; 754 interrupt-parent = <&gic>; 755 interrupts = <0 65 4>; 756 reg = <0x0 0xfe200000 0x40000>; 757 clock-names = "clk_xin", "clk_ahb"; 758 power-domains = <&pd_usb0>; 759 }; 760 761 usb1: usb@fe300000 { 762 compatible = "snps,dwc3"; 763 status = "disabled"; 764 interrupt-parent = <&gic>; 765 interrupts = <0 70 4>; 766 reg = <0x0 0xfe300000 0x40000>; 767 clock-names = "clk_xin", "clk_ahb"; 768 power-domains = <&pd_usb1>; 769 }; 770 771 watchdog0: watchdog@fd4d0000 { 772 compatible = "cdns,wdt-r1p2"; 773 status = "disabled"; 774 interrupt-parent = <&gic>; 775 interrupts = <0 113 1>; 776 reg = <0x0 0xfd4d0000 0x1000>; 777 timeout-sec = <10>; 778 }; 779 780 xilinx_drm: xilinx_drm { 781 compatible = "xlnx,drm"; 782 status = "disabled"; 783 xlnx,encoder-slave = <&xlnx_dp>; 784 xlnx,connector-type = "DisplayPort"; 785 xlnx,dp-sub = <&xlnx_dp_sub>; 786 planes { 787 xlnx,pixel-format = "rgb565"; 788 plane0 { 789 dmas = <&xlnx_dpdma 3>; 790 dma-names = "dma"; 791 }; 792 plane1 { 793 dmas = <&xlnx_dpdma 0>; 794 dma-names = "dma"; 795 }; 796 }; 797 }; 798 799 xlnx_dp: dp@43c00000 { 800 compatible = "xlnx,v-dp"; 801 status = "disabled"; 802 reg = <0x0 0xfd4a0000 0x1000>; 803 interrupts = <0 119 4>; 804 interrupt-parent = <&gic>; 805 clock-names = "aclk", "aud_clk"; 806 xlnx,dp-version = "v1.2"; 807 xlnx,max-lanes = <2>; 808 xlnx,max-link-rate = <540000>; 809 xlnx,max-bpc = <16>; 810 xlnx,enable-ycrcb; 811 xlnx,colormetry = "rgb"; 812 xlnx,bpc = <8>; 813 xlnx,audio-chan = <2>; 814 xlnx,dp-sub = <&xlnx_dp_sub>; 815 }; 816 817 xlnx_dp_snd_card: dp_snd_card { 818 compatible = "xlnx,dp-snd-card"; 819 status = "disabled"; 820 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; 821 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; 822 }; 823 824 xlnx_dp_snd_codec0: dp_snd_codec0 { 825 compatible = "xlnx,dp-snd-codec"; 826 status = "disabled"; 827 clock-names = "aud_clk"; 828 }; 829 830 xlnx_dp_snd_pcm0: dp_snd_pcm0 { 831 compatible = "xlnx,dp-snd-pcm"; 832 status = "disabled"; 833 dmas = <&xlnx_dpdma 4>; 834 dma-names = "tx"; 835 }; 836 837 xlnx_dp_snd_pcm1: dp_snd_pcm1 { 838 compatible = "xlnx,dp-snd-pcm"; 839 status = "disabled"; 840 dmas = <&xlnx_dpdma 5>; 841 dma-names = "tx"; 842 }; 843 844 xlnx_dp_sub: dp_sub@43c0a000 { 845 compatible = "xlnx,dp-sub"; 846 status = "disabled"; 847 reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; 848 reg-names = "blend", "av_buf", "aud"; 849 xlnx,output-fmt = "rgb"; 850 }; 851 852 xlnx_dpdma: dma@fd4c0000 { 853 compatible = "xlnx,dpdma"; 854 status = "disabled"; 855 reg = <0x0 0xfd4c0000 0x1000>; 856 interrupts = <0 122 4>; 857 interrupt-parent = <&gic>; 858 clock-names = "axi_clk"; 859 dma-channels = <6>; 860 #dma-cells = <1>; 861 dma-video0channel@43c10000 { 862 compatible = "xlnx,video0"; 863 }; 864 dma-video1channel@43c10000 { 865 compatible = "xlnx,video1"; 866 }; 867 dma-video2channel@43c10000 { 868 compatible = "xlnx,video2"; 869 }; 870 dma-graphicschannel@43c10000 { 871 compatible = "xlnx,graphics"; 872 }; 873 dma-audio0channel@43c10000 { 874 compatible = "xlnx,audio0"; 875 }; 876 dma-audio1channel@43c10000 { 877 compatible = "xlnx,audio1"; 878 }; 879 }; 880 }; 881}; 882