1/* 2 * Copyright (C) 2012 Altera <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include "skeleton.dtsi" 8#include <dt-bindings/reset/altr,rst-mgr.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 aliases { 15 ethernet0 = &gmac0; 16 ethernet1 = &gmac1; 17 serial0 = &uart0; 18 serial1 = &uart1; 19 timer0 = &timer0; 20 timer1 = &timer1; 21 timer2 = &timer2; 22 timer3 = &timer3; 23 spi0 = &qspi; 24 spi1 = &spi0; 25 spi2 = &spi1; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu@0 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <0>; 36 next-level-cache = <&L2>; 37 }; 38 cpu@1 { 39 compatible = "arm,cortex-a9"; 40 device_type = "cpu"; 41 reg = <1>; 42 next-level-cache = <&L2>; 43 }; 44 }; 45 46 intc: intc@fffed000 { 47 compatible = "arm,cortex-a9-gic"; 48 #interrupt-cells = <3>; 49 interrupt-controller; 50 reg = <0xfffed000 0x1000>, 51 <0xfffec100 0x100>; 52 }; 53 54 soc { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 compatible = "simple-bus"; 58 device_type = "soc"; 59 interrupt-parent = <&intc>; 60 ranges; 61 62 amba { 63 compatible = "arm,amba-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 68 pdma: pdma@ffe01000 { 69 compatible = "arm,pl330", "arm,primecell"; 70 reg = <0xffe01000 0x1000>; 71 interrupts = <0 104 4>, 72 <0 105 4>, 73 <0 106 4>, 74 <0 107 4>, 75 <0 108 4>, 76 <0 109 4>, 77 <0 110 4>, 78 <0 111 4>; 79 #dma-cells = <1>; 80 #dma-channels = <8>; 81 #dma-requests = <32>; 82 clocks = <&l4_main_clk>; 83 clock-names = "apb_pclk"; 84 }; 85 }; 86 87 can0: can@ffc00000 { 88 compatible = "bosch,d_can"; 89 reg = <0xffc00000 0x1000>; 90 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 91 clocks = <&can0_clk>; 92 status = "disabled"; 93 }; 94 95 can1: can@ffc01000 { 96 compatible = "bosch,d_can"; 97 reg = <0xffc01000 0x1000>; 98 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 99 clocks = <&can1_clk>; 100 status = "disabled"; 101 }; 102 103 clkmgr@ffd04000 { 104 compatible = "altr,clk-mgr"; 105 reg = <0xffd04000 0x1000>; 106 107 clocks { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 osc1: osc1 { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 }; 115 116 osc2: osc2 { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 }; 120 121 f2s_periph_ref_clk: f2s_periph_ref_clk { 122 #clock-cells = <0>; 123 compatible = "fixed-clock"; 124 }; 125 126 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 }; 130 131 main_pll: main_pll { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 #clock-cells = <0>; 135 compatible = "altr,socfpga-pll-clock"; 136 clocks = <&osc1>; 137 reg = <0x40>; 138 139 mpuclk: mpuclk { 140 #clock-cells = <0>; 141 compatible = "altr,socfpga-perip-clk"; 142 clocks = <&main_pll>; 143 div-reg = <0xe0 0 9>; 144 reg = <0x48>; 145 }; 146 147 mainclk: mainclk { 148 #clock-cells = <0>; 149 compatible = "altr,socfpga-perip-clk"; 150 clocks = <&main_pll>; 151 div-reg = <0xe4 0 9>; 152 reg = <0x4C>; 153 }; 154 155 dbg_base_clk: dbg_base_clk { 156 #clock-cells = <0>; 157 compatible = "altr,socfpga-perip-clk"; 158 clocks = <&main_pll>; 159 div-reg = <0xe8 0 9>; 160 reg = <0x50>; 161 }; 162 163 main_qspi_clk: main_qspi_clk { 164 #clock-cells = <0>; 165 compatible = "altr,socfpga-perip-clk"; 166 clocks = <&main_pll>; 167 reg = <0x54>; 168 }; 169 170 main_nand_sdmmc_clk: main_nand_sdmmc_clk { 171 #clock-cells = <0>; 172 compatible = "altr,socfpga-perip-clk"; 173 clocks = <&main_pll>; 174 reg = <0x58>; 175 }; 176 177 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { 178 #clock-cells = <0>; 179 compatible = "altr,socfpga-perip-clk"; 180 clocks = <&main_pll>; 181 reg = <0x5C>; 182 }; 183 }; 184 185 periph_pll: periph_pll { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 #clock-cells = <0>; 189 compatible = "altr,socfpga-pll-clock"; 190 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 191 reg = <0x80>; 192 193 emac0_clk: emac0_clk { 194 #clock-cells = <0>; 195 compatible = "altr,socfpga-perip-clk"; 196 clocks = <&periph_pll>; 197 reg = <0x88>; 198 }; 199 200 emac1_clk: emac1_clk { 201 #clock-cells = <0>; 202 compatible = "altr,socfpga-perip-clk"; 203 clocks = <&periph_pll>; 204 reg = <0x8C>; 205 }; 206 207 per_qspi_clk: per_qsi_clk { 208 #clock-cells = <0>; 209 compatible = "altr,socfpga-perip-clk"; 210 clocks = <&periph_pll>; 211 reg = <0x90>; 212 }; 213 214 per_nand_mmc_clk: per_nand_mmc_clk { 215 #clock-cells = <0>; 216 compatible = "altr,socfpga-perip-clk"; 217 clocks = <&periph_pll>; 218 reg = <0x94>; 219 }; 220 221 per_base_clk: per_base_clk { 222 #clock-cells = <0>; 223 compatible = "altr,socfpga-perip-clk"; 224 clocks = <&periph_pll>; 225 reg = <0x98>; 226 }; 227 228 h2f_usr1_clk: h2f_usr1_clk { 229 #clock-cells = <0>; 230 compatible = "altr,socfpga-perip-clk"; 231 clocks = <&periph_pll>; 232 reg = <0x9C>; 233 }; 234 }; 235 236 sdram_pll: sdram_pll { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 #clock-cells = <0>; 240 compatible = "altr,socfpga-pll-clock"; 241 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 242 reg = <0xC0>; 243 244 ddr_dqs_clk: ddr_dqs_clk { 245 #clock-cells = <0>; 246 compatible = "altr,socfpga-perip-clk"; 247 clocks = <&sdram_pll>; 248 reg = <0xC8>; 249 }; 250 251 ddr_2x_dqs_clk: ddr_2x_dqs_clk { 252 #clock-cells = <0>; 253 compatible = "altr,socfpga-perip-clk"; 254 clocks = <&sdram_pll>; 255 reg = <0xCC>; 256 }; 257 258 ddr_dq_clk: ddr_dq_clk { 259 #clock-cells = <0>; 260 compatible = "altr,socfpga-perip-clk"; 261 clocks = <&sdram_pll>; 262 reg = <0xD0>; 263 }; 264 265 h2f_usr2_clk: h2f_usr2_clk { 266 #clock-cells = <0>; 267 compatible = "altr,socfpga-perip-clk"; 268 clocks = <&sdram_pll>; 269 reg = <0xD4>; 270 }; 271 }; 272 273 mpu_periph_clk: mpu_periph_clk { 274 #clock-cells = <0>; 275 compatible = "altr,socfpga-perip-clk"; 276 clocks = <&mpuclk>; 277 fixed-divider = <4>; 278 }; 279 280 mpu_l2_ram_clk: mpu_l2_ram_clk { 281 #clock-cells = <0>; 282 compatible = "altr,socfpga-perip-clk"; 283 clocks = <&mpuclk>; 284 fixed-divider = <2>; 285 }; 286 287 l4_main_clk: l4_main_clk { 288 #clock-cells = <0>; 289 compatible = "altr,socfpga-gate-clk"; 290 clocks = <&mainclk>; 291 clk-gate = <0x60 0>; 292 }; 293 294 l3_main_clk: l3_main_clk { 295 #clock-cells = <0>; 296 compatible = "altr,socfpga-perip-clk"; 297 clocks = <&mainclk>; 298 fixed-divider = <1>; 299 }; 300 301 l3_mp_clk: l3_mp_clk { 302 #clock-cells = <0>; 303 compatible = "altr,socfpga-gate-clk"; 304 clocks = <&mainclk>; 305 div-reg = <0x64 0 2>; 306 clk-gate = <0x60 1>; 307 }; 308 309 l3_sp_clk: l3_sp_clk { 310 #clock-cells = <0>; 311 compatible = "altr,socfpga-gate-clk"; 312 clocks = <&mainclk>; 313 div-reg = <0x64 2 2>; 314 }; 315 316 l4_mp_clk: l4_mp_clk { 317 #clock-cells = <0>; 318 compatible = "altr,socfpga-gate-clk"; 319 clocks = <&mainclk>, <&per_base_clk>; 320 div-reg = <0x64 4 3>; 321 clk-gate = <0x60 2>; 322 }; 323 324 l4_sp_clk: l4_sp_clk { 325 #clock-cells = <0>; 326 compatible = "altr,socfpga-gate-clk"; 327 clocks = <&mainclk>, <&per_base_clk>; 328 div-reg = <0x64 7 3>; 329 clk-gate = <0x60 3>; 330 }; 331 332 dbg_at_clk: dbg_at_clk { 333 #clock-cells = <0>; 334 compatible = "altr,socfpga-gate-clk"; 335 clocks = <&dbg_base_clk>; 336 div-reg = <0x68 0 2>; 337 clk-gate = <0x60 4>; 338 }; 339 340 dbg_clk: dbg_clk { 341 #clock-cells = <0>; 342 compatible = "altr,socfpga-gate-clk"; 343 clocks = <&dbg_base_clk>; 344 div-reg = <0x68 2 2>; 345 clk-gate = <0x60 5>; 346 }; 347 348 dbg_trace_clk: dbg_trace_clk { 349 #clock-cells = <0>; 350 compatible = "altr,socfpga-gate-clk"; 351 clocks = <&dbg_base_clk>; 352 div-reg = <0x6C 0 3>; 353 clk-gate = <0x60 6>; 354 }; 355 356 dbg_timer_clk: dbg_timer_clk { 357 #clock-cells = <0>; 358 compatible = "altr,socfpga-gate-clk"; 359 clocks = <&dbg_base_clk>; 360 clk-gate = <0x60 7>; 361 }; 362 363 cfg_clk: cfg_clk { 364 #clock-cells = <0>; 365 compatible = "altr,socfpga-gate-clk"; 366 clocks = <&cfg_h2f_usr0_clk>; 367 clk-gate = <0x60 8>; 368 }; 369 370 h2f_user0_clk: h2f_user0_clk { 371 #clock-cells = <0>; 372 compatible = "altr,socfpga-gate-clk"; 373 clocks = <&cfg_h2f_usr0_clk>; 374 clk-gate = <0x60 9>; 375 }; 376 377 emac_0_clk: emac_0_clk { 378 #clock-cells = <0>; 379 compatible = "altr,socfpga-gate-clk"; 380 clocks = <&emac0_clk>; 381 clk-gate = <0xa0 0>; 382 }; 383 384 emac_1_clk: emac_1_clk { 385 #clock-cells = <0>; 386 compatible = "altr,socfpga-gate-clk"; 387 clocks = <&emac1_clk>; 388 clk-gate = <0xa0 1>; 389 }; 390 391 usb_mp_clk: usb_mp_clk { 392 #clock-cells = <0>; 393 compatible = "altr,socfpga-gate-clk"; 394 clocks = <&per_base_clk>; 395 clk-gate = <0xa0 2>; 396 div-reg = <0xa4 0 3>; 397 }; 398 399 spi_m_clk: spi_m_clk { 400 #clock-cells = <0>; 401 compatible = "altr,socfpga-gate-clk"; 402 clocks = <&per_base_clk>; 403 clk-gate = <0xa0 3>; 404 div-reg = <0xa4 3 3>; 405 }; 406 407 can0_clk: can0_clk { 408 #clock-cells = <0>; 409 compatible = "altr,socfpga-gate-clk"; 410 clocks = <&per_base_clk>; 411 clk-gate = <0xa0 4>; 412 div-reg = <0xa4 6 3>; 413 }; 414 415 can1_clk: can1_clk { 416 #clock-cells = <0>; 417 compatible = "altr,socfpga-gate-clk"; 418 clocks = <&per_base_clk>; 419 clk-gate = <0xa0 5>; 420 div-reg = <0xa4 9 3>; 421 }; 422 423 gpio_db_clk: gpio_db_clk { 424 #clock-cells = <0>; 425 compatible = "altr,socfpga-gate-clk"; 426 clocks = <&per_base_clk>; 427 clk-gate = <0xa0 6>; 428 div-reg = <0xa8 0 24>; 429 }; 430 431 h2f_user1_clk: h2f_user1_clk { 432 #clock-cells = <0>; 433 compatible = "altr,socfpga-gate-clk"; 434 clocks = <&h2f_usr1_clk>; 435 clk-gate = <0xa0 7>; 436 }; 437 438 sdmmc_clk: sdmmc_clk { 439 #clock-cells = <0>; 440 compatible = "altr,socfpga-gate-clk"; 441 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 442 clk-gate = <0xa0 8>; 443 clk-phase = <0 135>; 444 }; 445 446 nand_x_clk: nand_x_clk { 447 #clock-cells = <0>; 448 compatible = "altr,socfpga-gate-clk"; 449 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 450 clk-gate = <0xa0 9>; 451 }; 452 453 nand_clk: nand_clk { 454 #clock-cells = <0>; 455 compatible = "altr,socfpga-gate-clk"; 456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 457 clk-gate = <0xa0 10>; 458 fixed-divider = <4>; 459 }; 460 461 qspi_clk: qspi_clk { 462 #clock-cells = <0>; 463 compatible = "altr,socfpga-gate-clk"; 464 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 465 clk-gate = <0xa0 11>; 466 }; 467 }; 468 }; 469 470 gmac0: ethernet@ff700000 { 471 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 472 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 473 reg = <0xff700000 0x2000>; 474 interrupts = <0 115 4>; 475 interrupt-names = "macirq"; 476 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 477 clocks = <&emac0_clk>; 478 clock-names = "stmmaceth"; 479 resets = <&rst EMAC0_RESET>; 480 reset-names = "stmmaceth"; 481 snps,multicast-filter-bins = <256>; 482 snps,perfect-filter-entries = <128>; 483 status = "disabled"; 484 }; 485 486 gmac1: ethernet@ff702000 { 487 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 488 altr,sysmgr-syscon = <&sysmgr 0x60 2>; 489 reg = <0xff702000 0x2000>; 490 interrupts = <0 120 4>; 491 interrupt-names = "macirq"; 492 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 493 clocks = <&emac1_clk>; 494 clock-names = "stmmaceth"; 495 resets = <&rst EMAC1_RESET>; 496 reset-names = "stmmaceth"; 497 snps,multicast-filter-bins = <256>; 498 snps,perfect-filter-entries = <128>; 499 status = "disabled"; 500 }; 501 502 i2c0: i2c@ffc04000 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 compatible = "snps,designware-i2c"; 506 reg = <0xffc04000 0x1000>; 507 clocks = <&l4_sp_clk>; 508 interrupts = <0 158 0x4>; 509 status = "disabled"; 510 }; 511 512 i2c1: i2c@ffc05000 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "snps,designware-i2c"; 516 reg = <0xffc05000 0x1000>; 517 clocks = <&l4_sp_clk>; 518 interrupts = <0 159 0x4>; 519 status = "disabled"; 520 }; 521 522 i2c2: i2c@ffc06000 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 compatible = "snps,designware-i2c"; 526 reg = <0xffc06000 0x1000>; 527 clocks = <&l4_sp_clk>; 528 interrupts = <0 160 0x4>; 529 status = "disabled"; 530 }; 531 532 i2c3: i2c@ffc07000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "snps,designware-i2c"; 536 reg = <0xffc07000 0x1000>; 537 clocks = <&l4_sp_clk>; 538 interrupts = <0 161 0x4>; 539 status = "disabled"; 540 }; 541 542 gpio0: gpio@ff708000 { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 compatible = "snps,dw-apb-gpio"; 546 reg = <0xff708000 0x1000>; 547 clocks = <&per_base_clk>; 548 status = "disabled"; 549 550 porta: gpio-controller@0 { 551 compatible = "snps,dw-apb-gpio-port"; 552 gpio-controller; 553 #gpio-cells = <2>; 554 snps,nr-gpios = <29>; 555 reg = <0>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 interrupts = <0 164 4>; 559 }; 560 }; 561 562 gpio1: gpio@ff709000 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 compatible = "snps,dw-apb-gpio"; 566 reg = <0xff709000 0x1000>; 567 clocks = <&per_base_clk>; 568 status = "disabled"; 569 570 portb: gpio-controller@0 { 571 compatible = "snps,dw-apb-gpio-port"; 572 gpio-controller; 573 #gpio-cells = <2>; 574 snps,nr-gpios = <29>; 575 reg = <0>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 interrupts = <0 165 4>; 579 }; 580 }; 581 582 gpio2: gpio@ff70a000 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "snps,dw-apb-gpio"; 586 reg = <0xff70a000 0x1000>; 587 clocks = <&per_base_clk>; 588 status = "disabled"; 589 590 portc: gpio-controller@0 { 591 compatible = "snps,dw-apb-gpio-port"; 592 gpio-controller; 593 #gpio-cells = <2>; 594 snps,nr-gpios = <27>; 595 reg = <0>; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 interrupts = <0 166 4>; 599 }; 600 }; 601 602 sdr: sdr@ffc25000 { 603 compatible = "syscon"; 604 reg = <0xffc25000 0x1000>; 605 }; 606 607 sdramedac { 608 compatible = "altr,sdram-edac"; 609 altr,sdr-syscon = <&sdr>; 610 interrupts = <0 39 4>; 611 }; 612 613 L2: l2-cache@fffef000 { 614 compatible = "arm,pl310-cache"; 615 reg = <0xfffef000 0x1000>; 616 interrupts = <0 38 0x04>; 617 cache-unified; 618 cache-level = <2>; 619 arm,tag-latency = <1 1 1>; 620 arm,data-latency = <2 1 1>; 621 }; 622 623 mmc: dwmmc0@ff704000 { 624 compatible = "altr,socfpga-dw-mshc"; 625 reg = <0xff704000 0x1000>; 626 interrupts = <0 139 4>; 627 fifo-depth = <0x400>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 631 clock-names = "biu", "ciu"; 632 }; 633 634 qspi: spi@ff705000 { 635 compatible = "cadence,qspi"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 reg = <0xff705000 0x1000>, 639 <0xffa00000 0x1000>; 640 interrupts = <0 151 4>; 641 clocks = <&qspi_clk>; 642 ext-decoder = <0>; /* external decoder */ 643 num-cs = <4>; 644 fifo-depth = <128>; 645 sram-size = <128>; 646 bus-num = <2>; 647 status = "disabled"; 648 }; 649 650 spi0: spi@fff00000 { 651 compatible = "snps,dw-apb-ssi"; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 reg = <0xfff00000 0x1000>; 655 interrupts = <0 154 4>; 656 num-cs = <4>; 657 bus-num = <0>; 658 tx-dma-channel = <&pdma 16>; 659 rx-dma-channel = <&pdma 17>; 660 clocks = <&per_base_clk>; 661 status = "disabled"; 662 }; 663 664 spi1: spi@fff01000 { 665 compatible = "snps,dw-apb-ssi"; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 reg = <0xfff01000 0x1000>; 669 interrupts = <0 156 4>; 670 num-cs = <4>; 671 bus-num = <1>; 672 tx-dma-channel = <&pdma 20>; 673 rx-dma-channel = <&pdma 21>; 674 clocks = <&per_base_clk>; 675 status = "disabled"; 676 }; 677 678 /* Local timer */ 679 timer@fffec600 { 680 compatible = "arm,cortex-a9-twd-timer"; 681 reg = <0xfffec600 0x100>; 682 interrupts = <1 13 0xf04>; 683 clocks = <&mpu_periph_clk>; 684 }; 685 686 timer0: timer0@ffc08000 { 687 compatible = "snps,dw-apb-timer"; 688 interrupts = <0 167 4>; 689 reg = <0xffc08000 0x1000>; 690 clocks = <&l4_sp_clk>; 691 clock-names = "timer"; 692 }; 693 694 timer1: timer1@ffc09000 { 695 compatible = "snps,dw-apb-timer"; 696 interrupts = <0 168 4>; 697 reg = <0xffc09000 0x1000>; 698 clocks = <&l4_sp_clk>; 699 clock-names = "timer"; 700 }; 701 702 timer2: timer2@ffd00000 { 703 compatible = "snps,dw-apb-timer"; 704 interrupts = <0 169 4>; 705 reg = <0xffd00000 0x1000>; 706 clocks = <&osc1>; 707 clock-names = "timer"; 708 }; 709 710 timer3: timer3@ffd01000 { 711 compatible = "snps,dw-apb-timer"; 712 interrupts = <0 170 4>; 713 reg = <0xffd01000 0x1000>; 714 clocks = <&osc1>; 715 clock-names = "timer"; 716 }; 717 718 uart0: serial0@ffc02000 { 719 compatible = "snps,dw-apb-uart"; 720 reg = <0xffc02000 0x1000>; 721 interrupts = <0 162 4>; 722 reg-shift = <2>; 723 reg-io-width = <4>; 724 clocks = <&l4_sp_clk>; 725 }; 726 727 uart1: serial1@ffc03000 { 728 compatible = "snps,dw-apb-uart"; 729 reg = <0xffc03000 0x1000>; 730 interrupts = <0 163 4>; 731 reg-shift = <2>; 732 reg-io-width = <4>; 733 clocks = <&l4_sp_clk>; 734 }; 735 736 rst: rstmgr@ffd05000 { 737 #reset-cells = <1>; 738 compatible = "altr,rst-mgr"; 739 reg = <0xffd05000 0x1000>; 740 }; 741 742 usbphy0: usbphy@0 { 743 #phy-cells = <0>; 744 compatible = "usb-nop-xceiv"; 745 status = "okay"; 746 }; 747 748 usb0: usb@ffb00000 { 749 compatible = "snps,dwc2"; 750 reg = <0xffb00000 0xffff>; 751 interrupts = <0 125 4>; 752 clocks = <&usb_mp_clk>; 753 clock-names = "otg"; 754 phys = <&usbphy0>; 755 phy-names = "usb2-phy"; 756 status = "disabled"; 757 }; 758 759 usb1: usb@ffb40000 { 760 compatible = "snps,dwc2"; 761 reg = <0xffb40000 0xffff>; 762 interrupts = <0 128 4>; 763 clocks = <&usb_mp_clk>; 764 clock-names = "otg"; 765 phys = <&usbphy0>; 766 phy-names = "usb2-phy"; 767 status = "disabled"; 768 }; 769 770 watchdog0: watchdog@ffd02000 { 771 compatible = "snps,dw-wdt"; 772 reg = <0xffd02000 0x1000>; 773 interrupts = <0 171 4>; 774 clocks = <&osc1>; 775 status = "disabled"; 776 }; 777 778 watchdog1: watchdog@ffd03000 { 779 compatible = "snps,dw-wdt"; 780 reg = <0xffd03000 0x1000>; 781 interrupts = <0 172 4>; 782 clocks = <&osc1>; 783 status = "disabled"; 784 }; 785 786 sysmgr: sysmgr@ffd08000 { 787 compatible = "altr,sys-mgr", "syscon"; 788 reg = <0xffd08000 0x4000>; 789 }; 790 }; 791}; 792