1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rv1126-cru.h> 7#include <dt-bindings/power/rv1126-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip-system-status.h> 13#include "rv1126-dram-default-timing.dtsi" 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 compatible = "rockchip,rv1126"; 20 21 interrupt-parent = <&gic>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &uart2; 33 serial3 = &uart3; 34 serial4 = &uart4; 35 serial5 = &uart5; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 dphy0 = &csi_dphy0; 39 dphy1 = &csi_dphy1; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu0: cpu@f00 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf00>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 }; 54 55 cpu1: cpu@f01 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a7"; 58 reg = <0xf01>; 59 enable-method = "psci"; 60 clocks = <&cru ARMCLK>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@f02 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a7"; 67 reg = <0xf02>; 68 enable-method = "psci"; 69 clocks = <&cru ARMCLK>; 70 operating-points-v2 = <&cpu0_opp_table>; 71 }; 72 73 cpu3: cpu@f03 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a7"; 76 reg = <0xf03>; 77 enable-method = "psci"; 78 clocks = <&cru ARMCLK>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 }; 81 }; 82 83 cpu0_opp_table: cpu0-opp-table { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-408000000 { 88 opp-hz = /bits/ 64 <408000000>; 89 opp-microvolt = <800000 800000 945000>; 90 clock-latency-ns = <40000>; 91 opp-suspend; 92 }; 93 opp-600000000 { 94 opp-hz = /bits/ 64 <600000000>; 95 opp-microvolt = <800000 800000 945000>; 96 clock-latency-ns = <40000>; 97 }; 98 opp-816000000 { 99 opp-hz = /bits/ 64 <816000000>; 100 opp-microvolt = <800000 800000 945000>; 101 clock-latency-ns = <40000>; 102 }; 103 opp-1008000000 { 104 opp-hz = /bits/ 64 <1008000000>; 105 opp-microvolt = <800000 800000 945000>; 106 clock-latency-ns = <40000>; 107 }; 108 }; 109 110 arm-pmu { 111 compatible = "arm,cortex-a7-pmu"; 112 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 117 }; 118 119 display_subsystem: display-subsystem { 120 compatible = "rockchip,display-subsystem"; 121 ports = <&vop_out>; 122 status = "disabled"; 123 124 route { 125 route_dsi: route-dsi { 126 status = "disabled"; 127 logo,uboot = "logo.bmp"; 128 logo,kernel = "logo_kernel.bmp"; 129 logo,mode = "center"; 130 charge_logo,mode = "center"; 131 connect = <&vop_out_dsi>; 132 }; 133 134 route_rgb: route-rgb { 135 status = "disabled"; 136 logo,uboot = "logo.bmp"; 137 logo,kernel = "logo_kernel.bmp"; 138 logo,mode = "center"; 139 charge_logo,mode = "center"; 140 connect = <&vop_out_rgb>; 141 }; 142 }; 143 }; 144 145 fiq_debugger: fiq-debugger { 146 compatible = "rockchip,fiq-debugger"; 147 rockchip,serial-id = <2>; 148 rockchip,wake-irq = <0>; 149 rockchip,irq-mode-enable = <0>; 150 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 151 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 152 status = "disabled"; 153 }; 154 155 mpp_srv: mpp-srv { 156 compatible = "rockchip,mpp-service"; 157 rockchip,taskqueue-count = <3>; 158 rockchip,resetgroup-count = <3>; 159 status = "disabled"; 160 }; 161 162 psci { 163 compatible = "arm,psci-1.0"; 164 method = "smc"; 165 }; 166 167 rgb: rgb { 168 compatible = "rockchip,rv1126-rgb"; 169 status = "disabled"; 170 171 ports { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 port@0 { 176 reg = <0>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 180 rgb_in_vop: endpoint@0 { 181 reg = <0>; 182 remote-endpoint = <&vop_out_rgb>; 183 }; 184 }; 185 186 }; 187 }; 188 189 timer { 190 compatible = "arm,armv7-timer"; 191 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 192 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 193 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 194 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 195 clock-frequency = <24000000>; 196 }; 197 198 xin24m: oscillator { 199 compatible = "fixed-clock"; 200 clock-frequency = <24000000>; 201 clock-output-names = "xin24m"; 202 #clock-cells = <0>; 203 }; 204 205 grf: syscon@fe000000 { 206 compatible = "rockchip,rv1126-grf", "syscon"; 207 reg = <0xfe000000 0x20000>; 208 }; 209 210 pmugrf: syscon@fe020000 { 211 compatible = "rockchip,rv1126-pmugrf", "syscon"; 212 reg = <0xfe020000 0x1000>; 213 214 pmu_io_domains: io-domains { 215 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 216 }; 217 }; 218 219 qos_usb_host: qos@fe810008 { 220 compatible = "syscon"; 221 reg = <0xfe810008 0x20>; 222 }; 223 224 qos_usb_otg: qos@fe810088 { 225 compatible = "syscon"; 226 reg = <0xfe810088 0x20>; 227 }; 228 229 qos_npu: qos@fe850008 { 230 compatible = "syscon"; 231 reg = <0xfe850008 0x20>; 232 }; 233 234 qos_emmc: qos@fe860008 { 235 compatible = "syscon"; 236 reg = <0xfe860008 0x20>; 237 }; 238 239 qos_nandc: qos@fe860088 { 240 compatible = "syscon"; 241 reg = <0xe860088 0x20>; 242 }; 243 244 qos_sfc: qos@fe860208 { 245 compatible = "syscon"; 246 reg = <0xfe860208 0x20>; 247 }; 248 249 qos_sdmmc: qos@fe868008 { 250 compatible = "syscon"; 251 reg = <0xfe868008 0x20>; 252 }; 253 254 qos_sdio: qos@fe86c008 { 255 compatible = "syscon"; 256 reg = <0xfe86c008 0x20>; 257 }; 258 259 qos_vepu_rd0: qos@fe870008 { 260 compatible = "syscon"; 261 reg = <0xfe870008 0x20>; 262 }; 263 264 qos_vepu_rd1: qos@fe870088 { 265 compatible = "syscon"; 266 reg = <0xfe870088 0x20>; 267 }; 268 269 qos_vepu_wr: qos@fe870108 { 270 compatible = "syscon"; 271 reg = <0xfe870108 0x20>; 272 }; 273 274 qos_ispp_m0: qos@fe880018 { 275 compatible = "syscon"; 276 reg = <0xfe880018 0x20>; 277 }; 278 279 qos_ispp_m1: qos@fe880098 { 280 compatible = "syscon"; 281 reg = <0xfe880098 0x20>; 282 }; 283 284 qos_isp: qos@fe890008 { 285 compatible = "syscon"; 286 reg = <0xfe890008 0x20>; 287 }; 288 289 qos_cif_lite: qos@fe890088 { 290 compatible = "syscon"; 291 reg = <0xfe890088 0x20>; 292 }; 293 294 qos_cif: qos@fe890108 { 295 compatible = "syscon"; 296 reg = <0xfe890108 0x20>; 297 }; 298 299 qos_iep: qos@fe8a0008 { 300 compatible = "syscon"; 301 reg = <0xfe8a0008 0x20>; 302 }; 303 304 qos_rga_rd: qos@fe8a0088 { 305 compatible = "syscon"; 306 reg = <0xfe8a0088 0x20>; 307 }; 308 309 qos_rga_wr: qos@fe8a0108 { 310 compatible = "syscon"; 311 reg = <0xfe8a0108 0x20>; 312 }; 313 314 qos_vop: qos@fe8a0188 { 315 compatible = "syscon"; 316 reg = <0xfe8a0188 0x20>; 317 }; 318 319 qos_vdpu: qos@fe8b0008 { 320 compatible = "syscon"; 321 reg = <0xfe8b0008 0x20>; 322 }; 323 324 gic: interrupt-controller@feff0000 { 325 compatible = "arm,gic-400"; 326 interrupt-controller; 327 #interrupt-cells = <3>; 328 #address-cells = <0>; 329 330 reg = <0xfeff1000 0x1000>, 331 <0xfeff2000 0x2000>, 332 <0xfeff4000 0x2000>, 333 <0xfeff6000 0x2000>; 334 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 335 }; 336 337 pvtm@ff040000 { 338 compatible = "rockchip,rv1126-cpu-pvtm"; 339 reg = <0xff040000 0x100>; 340 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>; 341 clock-names = "clk", "pclk"; 342 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>; 343 reset-names = "clk", "pclk"; 344 }; 345 346 pmu: power-management@ff3e0000 { 347 compatible = "rockchip,rv1126-pmu", "syscon"; 348 reg = <0xff3e0000 0x1000>; 349 350 power: power-controller { 351 compatible = "rockchip,rv1126-power-controller"; 352 #power-domain-cells = <1>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 357 /* These power domains are grouped by VD_NPU */ 358 pd_npu@RV1126_PD_NPU { 359 reg = <RV1126_PD_NPU>; 360 clocks = <&cru ACLK_NPU>, 361 <&cru HCLK_NPU>, 362 <&cru PCLK_PDNPU>, 363 <&cru CLK_CORE_NPU>; 364 pm_qos = <&qos_npu>; 365 }; 366 /* These power domains are grouped by VD_VEPU */ 367 pd_vepu@RV1126_PD_VEPU { 368 reg = <RV1126_PD_VEPU>; 369 clocks = <&cru ACLK_VENC>, 370 <&cru HCLK_VENC>, 371 <&cru CLK_VENC_CORE>; 372 pm_qos = <&qos_vepu_rd0>, 373 <&qos_vepu_rd1>, 374 <&qos_vepu_wr>; 375 }; 376 /* These power domains are grouped by VD_LOGIC */ 377 pd_vi@RV1126_PD_VI { 378 reg = <RV1126_PD_VI>; 379 clocks = <&cru ACLK_ISP>, 380 <&cru HCLK_ISP>, 381 <&cru CLK_ISP>, 382 <&cru ACLK_CIF>, 383 <&cru HCLK_CIF>, 384 <&cru DCLK_CIF>, 385 <&cru CLK_CIF_OUT>, 386 <&cru CLK_MIPICSI_OUT>, 387 <&cru PCLK_CSIHOST>, 388 <&cru ACLK_CIFLITE>, 389 <&cru HCLK_CIFLITE>, 390 <&cru DCLK_CIFLITE>; 391 pm_qos = <&qos_isp>, 392 <&qos_cif_lite>, 393 <&qos_cif>; 394 }; 395 pd_vo@RV1126_PD_VO { 396 reg = <RV1126_PD_VO>; 397 clocks = <&cru ACLK_RGA>, 398 <&cru HCLK_RGA>, 399 <&cru CLK_RGA_CORE>, 400 <&cru ACLK_VOP>, 401 <&cru HCLK_VOP>, 402 <&cru DCLK_VOP>, 403 <&cru PCLK_DSIHOST>, 404 <&cru ACLK_IEP>, 405 <&cru HCLK_IEP>, 406 <&cru CLK_IEP_CORE>; 407 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 408 <&qos_vop>, <&qos_iep>; 409 }; 410 pd_ispp@RV1126_PD_ISPP { 411 reg = <RV1126_PD_ISPP>; 412 clocks = <&cru ACLK_ISPP>, 413 <&cru HCLK_ISPP>, 414 <&cru CLK_ISPP>; 415 pm_qos = <&qos_ispp_m0>, 416 <&qos_ispp_m1>; 417 }; 418 pd_vdpu@RV1126_PD_VDPU { 419 reg = <RV1126_PD_VDPU>; 420 clocks = <&cru ACLK_VDEC>, 421 <&cru HCLK_VDEC>, 422 <&cru CLK_VDEC_CORE>, 423 <&cru CLK_VDEC_CA>, 424 <&cru CLK_VDEC_HEVC_CA>, 425 <&cru ACLK_JPEG>, 426 <&cru HCLK_JPEG>; 427 pm_qos = <&qos_vdpu>; 428 }; 429 pd_nvm@RV1126_PD_NVM { 430 reg = <RV1126_PD_NVM>; 431 clocks = <&cru HCLK_EMMC>, 432 <&cru CLK_EMMC>, 433 <&cru HCLK_NANDC>, 434 <&cru CLK_NANDC>, 435 <&cru HCLK_SFC>, 436 <&cru HCLK_SFCXIP>, 437 <&cru SCLK_SFC>; 438 pm_qos = <&qos_emmc>, 439 <&qos_nandc>, 440 <&qos_sfc>, 441 <&qos_sdmmc>; 442 }; 443 pd_sdio@RV1126_PD_SDIO { 444 reg = <RV1126_PD_SDIO>; 445 clocks = <&cru HCLK_SDIO>, 446 <&cru CLK_SDIO>; 447 pm_qos = <&qos_sdio>; 448 }; 449 pd_usb@RV1126_PD_USB { 450 reg = <RV1126_PD_USB>; 451 clocks = <&cru HCLK_USBHOST>, 452 <&cru HCLK_USBHOST_ARB>, 453 <&cru CLK_USBHOST_UTMI_OHCI>, 454 <&cru ACLK_USBOTG>, 455 <&cru CLK_USBOTG_REF>; 456 pm_qos = <&qos_usb_host>, 457 <&qos_usb_otg>; 458 }; 459 }; 460 }; 461 462 i2c0: i2c@ff3f0000 { 463 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 464 reg = <0xff3f0000 0x1000>; 465 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 469 clock-names = "i2c", "pclk"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&i2c0_xfer>; 472 status = "disabled"; 473 }; 474 475 i2c2: i2c@ff400000 { 476 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 477 reg = <0xff400000 0x1000>; 478 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 482 clock-names = "i2c", "pclk"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c2_xfer>; 485 status = "disabled"; 486 }; 487 488 amba { 489 compatible = "simple-bus"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges; 493 494 dmac: dma-controller@ff4e0000 { 495 compatible = "arm,pl330", "arm,primecell"; 496 reg = <0xff4e0000 0x4000>; 497 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 499 #dma-cells = <1>; 500 clocks = <&cru ACLK_DMAC>; 501 clock-names = "apb_pclk"; 502 }; 503 }; 504 505 uart1: serial@ff410000 { 506 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 507 reg = <0xff410000 0x100>; 508 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 509 reg-shift = <2>; 510 reg-io-width = <4>; 511 dmas = <&dmac 7>, <&dmac 6>; 512 clock-frequency = <24000000>; 513 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 514 clock-names = "baudclk", "apb_pclk"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; 517 status = "disabled"; 518 }; 519 520 pwm0: pwm@ff430000 { 521 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 522 reg = <0xff430000 0x10>; 523 #pwm-cells = <3>; 524 pinctrl-names = "active"; 525 pinctrl-0 = <&pwm0m0_pins>; 526 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 527 clock-names = "pwm", "pclk"; 528 status = "disabled"; 529 }; 530 531 pwm1: pwm@ff430010 { 532 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 533 reg = <0xff430010 0x10>; 534 #pwm-cells = <3>; 535 pinctrl-names = "active"; 536 pinctrl-0 = <&pwm1m0_pins>; 537 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 538 clock-names = "pwm", "pclk"; 539 status = "disabled"; 540 }; 541 542 pwm2: pwm@ff430020 { 543 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 544 reg = <0xff430020 0x10>; 545 #pwm-cells = <3>; 546 pinctrl-names = "active"; 547 pinctrl-0 = <&pwm2m0_pins>; 548 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 549 clock-names = "pwm", "pclk"; 550 status = "disabled"; 551 }; 552 553 pwm3: pwm@ff430030 { 554 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 555 reg = <0xff430030 0x10>; 556 #pwm-cells = <3>; 557 pinctrl-names = "active"; 558 pinctrl-0 = <&pwm3m0_pins>; 559 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 560 clock-names = "pwm", "pclk"; 561 status = "disabled"; 562 }; 563 564 pwm4: pwm@ff440000 { 565 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 566 reg = <0xff440000 0x10>; 567 #pwm-cells = <3>; 568 pinctrl-names = "active"; 569 pinctrl-0 = <&pwm4m0_pins>; 570 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 571 clock-names = "pwm", "pclk"; 572 status = "disabled"; 573 }; 574 575 pwm5: pwm@ff440010 { 576 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 577 reg = <0xff440010 0x10>; 578 #pwm-cells = <3>; 579 pinctrl-names = "active"; 580 pinctrl-0 = <&pwm5m0_pins>; 581 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 582 clock-names = "pwm", "pclk"; 583 status = "disabled"; 584 }; 585 586 pwm6: pwm@ff440020 { 587 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 588 reg = <0xff440020 0x10>; 589 #pwm-cells = <3>; 590 pinctrl-names = "active"; 591 pinctrl-0 = <&pwm6m0_pins>; 592 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 593 clock-names = "pwm", "pclk"; 594 status = "disabled"; 595 }; 596 597 pwm7: pwm@ff440030 { 598 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 599 reg = <0xff440030 0x10>; 600 #pwm-cells = <3>; 601 pinctrl-names = "active"; 602 pinctrl-0 = <&pwm7m0_pins>; 603 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 604 clock-names = "pwm", "pclk"; 605 status = "disabled"; 606 }; 607 608 spi0: spi@ff450000 { 609 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 610 reg = <0xff450000 0x1000>; 611 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 614 clock-names = "spiclk", "apb_pclk"; 615 dmas = <&dmac 1>, <&dmac 0>; 616 dma-names = "tx", "rx"; 617 pinctrl-names = "default", "high_speed"; 618 pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>; 619 pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>; 620 status = "disabled"; 621 }; 622 623 pvtm@ff470000 { 624 compatible = "rockchip,rv1126-pmu-pvtm"; 625 reg = <0xff470000 0x100>; 626 clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>; 627 clock-names = "clk", "pclk"; 628 resets = <&cru SRST_PMUPVTM>, <&cru SRST_PMUPVTM_P>; 629 reset-names = "clk", "pclk"; 630 }; 631 632 pmucru: clock-controller@ff480000 { 633 compatible = "rockchip,rv1126-pmucru"; 634 reg = <0xff480000 0x1000>; 635 rockchip,grf = <&grf>; 636 #clock-cells = <1>; 637 #reset-cells = <1>; 638 }; 639 640 cru: clock-controller@ff490000 { 641 compatible = "rockchip,rv1126-cru"; 642 reg = <0xff490000 0x1000>; 643 rockchip,grf = <&grf>; 644 #clock-cells = <1>; 645 #reset-cells = <1>; 646 647 assigned-clocks = 648 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 649 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 650 <&cru PLL_HPLL>, <&cru ARMCLK>, 651 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 652 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 653 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 654 <&cru HCLK_PDCORE_NIU>; 655 assigned-clock-rates = 656 <32768>, <1188000000>, 657 <100000000>, <1000000000>, 658 <1600000000>, <600000000>, 659 <500000000>, <200000000>, 660 <100000000>, <300000000>, 661 <200000000>, <150000000>, 662 <200000000>; 663 assigned-clock-parents = 664 <&pmucru CLK_OSC0_DIV32K>; 665 }; 666 667 csi_dphy0: csi-dphy@ff4b0000 { 668 compatible = "rockchip,rv1126-csi-dphy"; 669 reg = <0xff4b0000 0x8000>; 670 clocks = <&cru PCLK_CSIPHY0>; 671 clock-names = "pclk"; 672 rockchip,grf = <&grf>; 673 status = "disabled"; 674 }; 675 676 csi_dphy1: csi-dphy@ff4b8000 { 677 compatible = "rockchip,rv1126-csi-dphy"; 678 reg = <0xff4b8000 0x8000>; 679 clocks = <&cru PCLK_CSIPHY1>; 680 clock-names = "pclk"; 681 rockchip,grf = <&grf>; 682 status = "disabled"; 683 }; 684 685 u2phy0: usb2-phy@ff4c0000 { 686 compatible = "rockchip,rv1126-usb2phy"; 687 reg = <0xff4c0000 0x8000>; 688 clocks = <&cru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>; 689 clock-names = "phyclk", "pclk"; 690 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>; 691 reset-names = "u2phy", "u2phy-apb"; 692 #clock-cells = <0>; 693 clock-output-names = "usb480m_phy0"; 694 status = "disabled"; 695 696 u2phy_otg: otg-port { 697 #phy-cells = <0>; 698 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "otg-bvalid", "otg-id", 703 "linestate", "disconnect"; 704 status = "disabled"; 705 }; 706 }; 707 708 u2phy1: usb2-phy@ff4c8000 { 709 compatible = "rockchip,rv1126-usb2phy"; 710 reg = <0xff4c8000 0x8000>; 711 clocks = <&cru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>; 712 clock-names = "phyclk", "pclk"; 713 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>; 714 reset-names = "u2phy", "u2phy-apb"; 715 #clock-cells = <0>; 716 clock-output-names = "usb480m_phy1"; 717 status = "disabled"; 718 719 u2phy_host: host-port { 720 #phy-cells = <0>; 721 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-names = "linestate", "disconnect"; 724 status = "disabled"; 725 }; 726 }; 727 728 mipi_dphy: mipi-dphy@ff4d0000 { 729 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy"; 730 reg = <0xff4d0000 0x500>; 731 clocks = <&cru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>; 732 clock-names = "ref", "pclk"; 733 clock-output-names = "mipi_dphy_pll"; 734 #clock-cells = <0>; 735 resets = <&cru SRST_DSIPHY_P>; 736 reset-names = "apb"; 737 #phy-cells = <0>; 738 rockchip,grf = <&grf>; 739 status = "disabled"; 740 }; 741 742 crypto: crypto@ff500000 { 743 compatible = "rockchip,rv1126-crypto"; 744 reg = <0xff500000 0x10000>; 745 clock-names = "sclk_crypto", "sclk_crypto_apk"; 746 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>; 747 clock-frequency = <200000000>, <300000000>; 748 status = "disabled"; 749 }; 750 751 i2c1: i2c@ff510000 { 752 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 753 reg = <0xff510000 0x1000>; 754 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 758 clock-names = "i2c", "pclk"; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&i2c1_xfer>; 761 status = "disabled"; 762 }; 763 764 i2c3: i2c@ff520000 { 765 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 766 reg = <0xff520000 0x1000>; 767 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 771 clock-names = "i2c", "pclk"; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&i2c3m0_xfer>; 774 status = "disabled"; 775 }; 776 777 i2c4: i2c@ff530000 { 778 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 779 reg = <0xff530000 0x1000>; 780 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 784 clock-names = "i2c", "pclk"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&i2c4m0_xfer>; 787 status = "disabled"; 788 }; 789 790 i2c5: i2c@ff540000 { 791 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 792 reg = <0xff540000 0x1000>; 793 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 797 clock-names = "i2c", "pclk"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&i2c5m0_xfer>; 800 status = "disabled"; 801 }; 802 803 pwm8: pwm@ff550000 { 804 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 805 reg = <0xff550000 0x10>; 806 #pwm-cells = <3>; 807 pinctrl-names = "active"; 808 pinctrl-0 = <&pwm8m0_pins>; 809 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 810 clock-names = "pwm", "pclk"; 811 status = "disabled"; 812 }; 813 814 pwm9: pwm@ff550010 { 815 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 816 reg = <0xff550010 0x10>; 817 #pwm-cells = <3>; 818 pinctrl-names = "active"; 819 pinctrl-0 = <&pwm9m0_pins>; 820 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 821 clock-names = "pwm", "pclk"; 822 status = "disabled"; 823 }; 824 825 pwm10: pwm@ff550020 { 826 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 827 reg = <0xff550020 0x10>; 828 #pwm-cells = <3>; 829 pinctrl-names = "active"; 830 pinctrl-0 = <&pwm10m0_pins>; 831 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 832 clock-names = "pwm", "pclk"; 833 status = "disabled"; 834 }; 835 836 pwm11: pwm@ff550030 { 837 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 838 reg = <0xff550030 0x10>; 839 #pwm-cells = <3>; 840 pinctrl-names = "active"; 841 pinctrl-0 = <&pwm11m0_pins>; 842 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 843 clock-names = "pwm", "pclk"; 844 status = "disabled"; 845 }; 846 847 uart0: serial@ff560000 { 848 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 849 reg = <0xff560000 0x100>; 850 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 851 reg-shift = <2>; 852 reg-io-width = <4>; 853 dmas = <&dmac 5>, <&dmac 4>; 854 clock-frequency = <24000000>; 855 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 856 clock-names = "baudclk", "apb_pclk"; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; 859 status = "disabled"; 860 }; 861 862 uart2: serial@ff570000 { 863 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 864 reg = <0xff570000 0x100>; 865 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 866 reg-shift = <2>; 867 reg-io-width = <4>; 868 dmas = <&dmac 9>, <&dmac 8>; 869 clock-frequency = <24000000>; 870 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 871 clock-names = "baudclk", "apb_pclk"; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&uart2m1_xfer>; 874 status = "disabled"; 875 }; 876 877 uart3: serial@ff580000 { 878 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 879 reg = <0xff580000 0x100>; 880 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 881 reg-shift = <2>; 882 reg-io-width = <4>; 883 dmas = <&dmac 11>, <&dmac 10>; 884 clock-frequency = <24000000>; 885 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 886 clock-names = "baudclk", "apb_pclk"; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>; 889 status = "disabled"; 890 }; 891 892 uart4: serial@ff590000 { 893 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 894 reg = <0xff590000 0x100>; 895 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 896 reg-shift = <2>; 897 reg-io-width = <4>; 898 dmas = <&dmac 13>, <&dmac 12>; 899 clock-frequency = <24000000>; 900 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 901 clock-names = "baudclk", "apb_pclk"; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; 904 status = "disabled"; 905 }; 906 907 uart5: serial@ff5a0000 { 908 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 909 reg = <0xff5a0000 0x100>; 910 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 911 reg-shift = <2>; 912 reg-io-width = <4>; 913 dmas = <&dmac 15>, <&dmac 14>; 914 clock-frequency = <24000000>; 915 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 916 clock-names = "baudclk", "apb_pclk"; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 919 status = "disabled"; 920 }; 921 922 spi1: spi@ff5b0000 { 923 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; 924 reg = <0xff5b0000 0x1000>; 925 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 928 clock-names = "spiclk", "apb_pclk"; 929 dmas = <&dmac 3>, <&dmac 2>; 930 dma-names = "tx", "rx"; 931 pinctrl-names = "default", "high_speed"; 932 pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>; 933 pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>; 934 status = "disabled"; 935 }; 936 937 otp: otp@ff5c0000 { 938 compatible = "rockchip,rv1126-otp"; 939 reg = <0xff5c0000 0x1000>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>; 943 clock-names = "otp", "apb_pclk"; 944 status = "disabled"; 945 946 /* Data cells */ 947 otp_id: id@7 { 948 reg = <0x07 0x10>; 949 }; 950 cpu_leakage: cpu-leakage@17 { 951 reg = <0x17 0x1>; 952 }; 953 logic_leakage: logic-leakage@18 { 954 reg = <0x18 0x1>; 955 }; 956 npu_leakage: npu-leakage@19 { 957 reg = <0x19 0x1>; 958 }; 959 }; 960 961 secure_otp: secure_otp@0xff5d0000 { 962 compatible = "rockchip,rv1126-secure-otp"; 963 reg = <0xff5d0000 0x4000>; 964 secure_conf = <0xfe0a0008>; 965 }; 966 967 saradc: saradc@ff5e0000 { 968 compatible = "rockchip,rk3399-saradc"; 969 reg = <0xff5e0000 0x100>; 970 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 971 #io-channel-cells = <1>; 972 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 973 clock-names = "saradc", "apb_pclk"; 974 resets = <&cru SRST_SARADC_P>; 975 reset-names = "saradc-apb"; 976 status = "disabled"; 977 }; 978 979 cpu_tsadc: tsadc@ff5f0000 { 980 compatible = "rockchip,rv1126-tsadc"; 981 reg = <0xff5f0000 0x100>; 982 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 983 assigned-clocks = <&cru CLK_CPU_TSADC>; 984 assigned-clock-rates = <600000>; 985 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>, 986 <&cru CLK_CPU_TSADCPHY>; 987 clock-names = "tsadc", "apb_pclk", "phy_clk"; 988 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>, 989 <&cru SRST_CPU_TSADCPHY>; 990 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 991 rockchip,hw-tshut-temp = <120000>; 992 #thermal-sensor-cells = <1>; 993 status = "disabled"; 994 }; 995 996 npu_tsadc: tsadc@ff5f8000 { 997 compatible = "rockchip,rv1126-tsadc"; 998 reg = <0xff5f8000 0x100>; 999 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1000 assigned-clocks = <&cru CLK_NPU_TSADC>; 1001 assigned-clock-rates = <600000>; 1002 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>, 1003 <&cru CLK_NPU_TSADCPHY>; 1004 clock-names = "tsadc", "apb_pclk", "phy_clk"; 1005 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>, 1006 <&cru SRST_NPU_TSADCPHY>; 1007 reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; 1008 rockchip,hw-tshut-temp = <120000>; 1009 #thermal-sensor-cells = <1>; 1010 status = "disabled"; 1011 }; 1012 1013 can: can@ff610000 { 1014 compatible = "rockchip,can-1.0"; 1015 reg = <0xff610000 0x100>; 1016 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1017 assigned-clocks = <&cru CLK_CAN>; 1018 assigned-clock-rates = <100000000>; 1019 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>; 1020 clock-names = "baudclk", "apb_pclk"; 1021 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>; 1022 reset-names = "can", "can-apb"; 1023 status = "disabled"; 1024 }; 1025 1026 wdt: watchdog@ff680000 { 1027 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; 1028 reg = <0xff680000 0x100>; 1029 clocks = <&cru PCLK_WDT>; 1030 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1031 status = "disabled"; 1032 }; 1033 1034 mailbox: mailbox@ff6a0000 { 1035 compatible = "rockchip,rv1126-mailbox", 1036 "rockchip,rk3368-mailbox"; 1037 reg = <0xff6a0000 0x1000>; 1038 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru PCLK_MAILBOX>; 1040 clock-names = "pclk_mailbox"; 1041 #mbox-cells = <1>; 1042 status = "disabled"; 1043 }; 1044 1045 hw_decompress: decompress@ff6c0000 { 1046 compatible = "rockchip,hw-decompress"; 1047 reg = <0xff6c0000 0x10000>; 1048 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1050 clock-names = "aclk", "dclk", "pclk"; 1051 soft-reset-addr = <0xff490314>; 1052 status = "disabled"; 1053 }; 1054 1055 i2s0_8ch: i2s@ff800000 { 1056 compatible = "rockchip,rv1126-i2s-tdm"; 1057 reg = <0xff800000 0x1000>; 1058 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>; 1060 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1061 dmas = <&dmac 20>, <&dmac 19>; 1062 dma-names = "tx", "rx"; 1063 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>; 1064 reset-names = "tx-m", "rx-m"; 1065 rockchip,cru = <&cru>; 1066 rockchip,grf = <&grf>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&i2s0m0_sclk_tx 1069 &i2s0m0_sclk_rx 1070 &i2s0m0_lrck_tx 1071 &i2s0m0_lrck_rx 1072 &i2s0m0_sdi0 1073 &i2s0m0_sdo0 1074 &i2s0m0_sdo1_sdi3 1075 &i2s0m0_sdo2_sdi2 1076 &i2s0m0_sdo3_sdi1>; 1077 status = "disabled"; 1078 }; 1079 1080 i2s1_2ch: i2s@ff810000 { 1081 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1082 reg = <0xff810000 0x1000>; 1083 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>; 1085 clock-names = "i2s_clk", "i2s_hclk"; 1086 dmas = <&dmac 22>, <&dmac 21>; 1087 dma-names = "tx", "rx"; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&i2s1m0_sclk 1090 &i2s1m0_lrck 1091 &i2s1m0_sdi 1092 &i2s1m0_sdo>; 1093 status = "disabled"; 1094 }; 1095 1096 i2s2_2ch: i2s@ff820000 { 1097 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; 1098 reg = <0xff820000 0x1000>; 1099 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>; 1101 clock-names = "i2s_clk", "i2s_hclk"; 1102 dmas = <&dmac 24>, <&dmac 23>; 1103 dma-names = "tx", "rx"; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&i2s2m0_sclk 1106 &i2s2m0_lrck 1107 &i2s2m0_sdi 1108 &i2s2m0_sdo>; 1109 status = "disabled"; 1110 }; 1111 1112 pdm: pdm@ff830000 { 1113 compatible = "rockchip,rv1126-pdm", "rockchip,pdm"; 1114 reg = <0xff830000 0x1000>; 1115 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1116 clock-names = "pdm_clk", "pdm_hclk"; 1117 dmas = <&dmac 25>; 1118 dma-names = "rx"; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&pdmm0_clk 1121 &pdmm0_clk1 1122 &pdmm0_sdi0 1123 &pdmm0_sdi1 1124 &pdmm0_sdi2 1125 &pdmm0_sdi3>; 1126 status = "disabled"; 1127 }; 1128 1129 audpwm: audpwm@ff840000 { 1130 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1"; 1131 reg = <0xff840000 0x1000>; 1132 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 1133 clock-names = "clk", "hclk"; 1134 dmas = <&dmac 26>; 1135 dma-names = "tx"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&audpwmm0_pins>; 1138 rockchip,sample-width-bits = <11>; 1139 rockchip,interpolat-points = <1>; 1140 status = "disabled"; 1141 }; 1142 1143 dfi: dfi@ff9c0000 { 1144 reg = <0xff9c0000 0x400>; 1145 compatible = "rockchip,rv1126-dfi"; 1146 rockchip,pmugrf = <&pmugrf>; 1147 status = "disabled"; 1148 }; 1149 1150 dmc: dmc { 1151 compatible = "rockchip,rv1126-dmc"; 1152 devfreq-events = <&dfi>; 1153 clocks = <&cru SCLK_DDRCLK>; 1154 clock-names = "dmc_clk"; 1155 operating-points-v2 = <&dmc_opp_table>; 1156 ddr_timing = <&ddr_timing>; 1157 upthreshold = <40>; 1158 downdifferential = <20>; 1159 system-status-freq = < 1160 /*system status freq(KHz)*/ 1161 SYS_STATUS_NORMAL 924000 1162 SYS_STATUS_REBOOT 450000 1163 SYS_STATUS_SUSPEND 328000 1164 SYS_STATUS_VIDEO_1080P 924000 1165 SYS_STATUS_BOOST 924000 1166 SYS_STATUS_ISP 924000 1167 SYS_STATUS_PERFORMANCE 924000 1168 >; 1169 auto-min-freq = <328000>; 1170 auto-freq-en = <0>; 1171 #cooling-cells = <2>; 1172 status = "disabled"; 1173 }; 1174 1175 dmc_opp_table: dmc-opp-table { 1176 compatible = "operating-points-v2"; 1177 1178 opp-328000000 { 1179 opp-hz = /bits/ 64 <328000000>; 1180 opp-microvolt = <800000>; 1181 }; 1182 opp-450000000 { 1183 opp-hz = /bits/ 64 <450000000>; 1184 opp-microvolt = <800000>; 1185 }; 1186 opp-664000000 { 1187 opp-hz = /bits/ 64 <664000000>; 1188 opp-microvolt = <800000>; 1189 }; 1190 opp-924000000 { 1191 opp-hz = /bits/ 64 <924000000>; 1192 opp-microvolt = <800000>; 1193 }; 1194 opp-1056000000 { 1195 opp-hz = /bits/ 64 <1056000000>; 1196 opp-microvolt = <800000>; 1197 status = "disabled"; 1198 }; 1199 }; 1200 1201 vop: vop@ffb00000 { 1202 compatible = "rockchip,rv1126-vop"; 1203 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 1204 reg-names = "regs", "gamma_lut"; 1205 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 1207 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1208 iommus = <&vop_mmu>; 1209 status = "disabled"; 1210 1211 vop_out: port { 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 vop_out_rgb: endpoint@0 { 1216 reg = <0>; 1217 remote-endpoint = <&rgb_in_vop>; 1218 }; 1219 1220 vop_out_dsi: endpoint@1 { 1221 reg = <1>; 1222 remote-endpoint = <&dsi_in_vop>; 1223 }; 1224 }; 1225 }; 1226 1227 vop_mmu: iommu@ffb00f00 { 1228 compatible = "rockchip,iommu"; 1229 reg = <0xffb00f00 0x100>; 1230 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "vop_mmu"; 1232 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1233 clock-names = "aclk", "iface"; 1234 #iommu-cells = <0>; 1235 rockchip,disable-device-link-resume; 1236 status = "disabled"; 1237 }; 1238 1239 dsi: dsi@ffb30000 { 1240 compatible = "rockchip,rv1126-mipi-dsi"; 1241 reg = <0xffb30000 0x500>; 1242 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>; 1244 clock-names = "pclk", "hs_clk"; 1245 resets = <&cru SRST_DSIHOST_P>; 1246 reset-names = "apb"; 1247 phys = <&mipi_dphy>; 1248 phy-names = "mipi_dphy"; 1249 rockchip,grf = <&grf>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 1254 ports { 1255 port { 1256 dsi_in_vop: endpoint { 1257 remote-endpoint = <&vop_out_dsi>; 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 rkisp: rkisp@ffb50000 { 1264 compatible = "rockchip,rv1126-rkisp"; 1265 reg = <0xffb50000 0x10000>; 1266 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1270 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1271 <&cru CLK_ISP>; 1272 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1273 power-domains = <&power RV1126_PD_VI>; 1274 iommus = <&rkisp_mmu>; 1275 status = "disabled"; 1276 }; 1277 1278 rkisp_mmu: iommu@ffb51a00 { 1279 compatible = "rockchip,iommu"; 1280 reg = <0xffb51a00 0x100>; 1281 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1282 interrupt-names = "isp_mmu"; 1283 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1284 clock-names = "aclk", "iface"; 1285 power-domains = <&power RV1126_PD_VI>; 1286 #iommu-cells = <0>; 1287 rockchip,disable-mmu-reset; 1288 status = "disabled"; 1289 }; 1290 1291 rkispp: rkispp@ffb60000 { 1292 compatible = "rockchip,rv1126-rkispp"; 1293 reg = <0xffb60000 0x20000>; 1294 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1296 interrupt-names = "ispp_irq", "fec_irq"; 1297 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>, 1298 <&cru CLK_ISPP>; 1299 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 1300 power-domains = <&power RV1126_PD_ISPP>; 1301 iommus = <&rkispp_mmu>; 1302 status = "disabled"; 1303 }; 1304 1305 rkispp_mmu: iommu@ffb60e00 { 1306 compatible = "rockchip,iommu"; 1307 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>; 1308 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1311 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1"; 1312 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>; 1313 clock-names = "aclk", "iface"; 1314 power-domains = <&power RV1126_PD_ISPP>; 1315 #iommu-cells = <0>; 1316 rockchip,disable-mmu-reset; 1317 status = "disabled"; 1318 }; 1319 1320 rkvenc: rkvenc@ffbb0000 { 1321 compatible = "rockchip,rkv-encoder-v1"; 1322 reg = <0xffbb0000 0x400>; 1323 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1324 interrupt-names = "irq_enc"; 1325 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>, 1326 <&cru CLK_VENC_CORE>; 1327 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1328 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>, 1329 <&cru SRST_VENC_CORE>; 1330 reset-names = "video_a", "video_h", "video_core"; 1331 iommus = <&rkvenc_mmu>; 1332 node-name = "rkvenc"; 1333 rockchip,srv = <&mpp_srv>; 1334 rockchip,taskqueue-node = <2>; 1335 rockchip,resetgroup-node = <2>; 1336 power-domains = <&power RV1126_PD_VEPU>; 1337 status = "disabled"; 1338 }; 1339 1340 rkvenc_mmu: iommu@ffbb0f00 { 1341 compatible = "rockchip,iommu"; 1342 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>; 1343 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1345 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1346 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>; 1347 clock-names = "aclk", "iface"; 1348 rockchip,disable-mmu-reset; 1349 #iommu-cells = <0>; 1350 power-domains = <&power RV1126_PD_VEPU>; 1351 status = "disabled"; 1352 }; 1353 1354 pvtm@ffc00000 { 1355 compatible = "rockchip,rv1126-npu-pvtm"; 1356 reg = <0xffc00000 0x100>; 1357 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>; 1358 clock-names = "clk", "pclk"; 1359 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>; 1360 reset-names = "clk", "pclk"; 1361 }; 1362 1363 gmac: ethernet@ffc40000 { 1364 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 1365 reg = <0xffc40000 0x0ffff>; 1366 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1368 interrupt-names = "macirq", "eth_wake_irq"; 1369 rockchip,grf = <&grf>; 1370 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 1371 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 1372 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 1373 <&cru RGMII_MODE_CLK>, <&cru CLK_GMAC_PTPREF>; 1374 clock-names = "stmmaceth", "mac_clk_rx", 1375 "mac_clk_tx", "clk_mac_refout", 1376 "aclk_mac", "pclk_mac", 1377 "clk_mac_speed", "ptp_ref"; 1378 resets = <&cru SRST_GMAC_A>; 1379 reset-names = "stmmaceth"; 1380 1381 snps,mixed-burst; 1382 snps,tso; 1383 1384 snps,axi-config = <&stmmac_axi_setup>; 1385 snps,mtl-rx-config = <&mtl_rx_setup>; 1386 snps,mtl-tx-config = <&mtl_tx_setup>; 1387 status = "disabled"; 1388 1389 mdio: mdio { 1390 compatible = "snps,dwmac-mdio"; 1391 #address-cells = <0x1>; 1392 #size-cells = <0x0>; 1393 }; 1394 1395 stmmac_axi_setup: stmmac-axi-config { 1396 snps,wr_osr_lmt = <4>; 1397 snps,rd_osr_lmt = <8>; 1398 snps,blen = <0 0 0 0 16 8 4>; 1399 }; 1400 1401 mtl_rx_setup: rx-queues-config { 1402 snps,rx-queues-to-use = <1>; 1403 queue0 {}; 1404 }; 1405 1406 mtl_tx_setup: tx-queues-config { 1407 snps,tx-queues-to-use = <1>; 1408 queue0 {}; 1409 }; 1410 }; 1411 1412 emmc: dwmmc@ffc50000 { 1413 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1414 reg = <0xffc50000 0x4000>; 1415 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 1417 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1418 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1419 fifo-depth = <0x100>; 1420 max-frequency = <200000000>; 1421 status = "disabled"; 1422 }; 1423 1424 sdmmc: dwmmc@ffc60000 { 1425 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1426 reg = <0xffc60000 0x4000>; 1427 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1428 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 1429 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1430 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1431 fifo-depth = <0x100>; 1432 max-frequency = <100000000>; 1433 pinctrl-names = "default"; 1434 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_det &sdmmc1_bus4>; 1435 status = "disabled"; 1436 }; 1437 1438 sdio: dwmmc@ffc70000 { 1439 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 1440 reg = <0xffc70000 0x4000>; 1441 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1442 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 1443 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1444 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1445 fifo-depth = <0x100>; 1446 max-frequency = <150000000>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; 1449 status = "disabled"; 1450 }; 1451 1452 nandc: nandc@ffc80000 { 1453 compatible = "rockchip,rk-nandc"; 1454 reg = <0xffc80000 0x4000>; 1455 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1456 nandc_id = <0>; 1457 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>; 1458 clock-names = "clk_nandc", "hclk_nandc"; 1459 status = "disabled"; 1460 }; 1461 1462 sfc: sfc@ffc90000 { 1463 compatible = "rockchip,sfc"; 1464 reg = <0xffc90000 0x4000>; 1465 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1467 clock-names = "clk_sfc", "hclk_sfc"; 1468 assigned-clocks = <&cru SCLK_SFC>; 1469 assigned-clock-rates = <80000000>; 1470 status = "disabled"; 1471 }; 1472 1473 usbdrd: usb0 { 1474 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3"; 1475 #address-cells = <1>; 1476 #size-cells = <1>; 1477 ranges; 1478 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>; 1479 clock-names = "ref_clk", "bus_clk"; 1480 status = "disabled"; 1481 1482 usbdrd_dwc3: dwc3@ffd00000 { 1483 compatible = "snps,dwc3"; 1484 reg = <0xffd00000 0x100000>; 1485 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1486 dr_mode = "otg"; 1487 maximum-speed = "high-speed"; 1488 phys = <&u2phy_otg>; 1489 phy-names = "usb2-phy"; 1490 phy_type = "utmi_wide"; 1491 power-domains = <&power RV1126_PD_USB>; 1492 resets = <&cru SRST_USBOTG_A>; 1493 reset-names = "usb3-otg"; 1494 snps,dis_enblslpm_quirk; 1495 snps,dis-u2-freeclk-exists-quirk; 1496 snps,dis_u2_susphy_quirk; 1497 snps,dis-del-phy-power-chg-quirk; 1498 snps,tx-ipgap-linecheck-dis-quirk; 1499 snps,xhci-trb-ent-quirk; 1500 status = "disabled"; 1501 }; 1502 }; 1503 1504 usb_host0_ehci: usb@ffe00000 { 1505 compatible = "generic-ehci"; 1506 reg = <0xffe00000 0x20000>; 1507 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1508 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 1509 <&u2phy1>; 1510 clock-names = "usbhost", "arbiter", "utmi"; 1511 phys = <&u2phy_host>; 1512 phy-names = "usb"; 1513 power-domains = <&power RV1126_PD_USB>; 1514 status = "disabled"; 1515 }; 1516 1517 usb_host0_ohci: usb@ffe10000 { 1518 compatible = "generic-ohci"; 1519 reg = <0xffe20000 0x20000>; 1520 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, 1522 <&u2phy1>; 1523 clock-names = "usbhost", "arbiter", "utmi"; 1524 phys = <&u2phy_host>; 1525 phy-names = "usb"; 1526 power-domains = <&power RV1126_PD_USB>; 1527 status = "disabled"; 1528 }; 1529 1530 pinctrl: pinctrl { 1531 compatible = "rockchip,rv1126-pinctrl"; 1532 rockchip,grf = <&grf>; 1533 rockchip,pmu = <&pmugrf>; 1534 #address-cells = <1>; 1535 #size-cells = <1>; 1536 ranges; 1537 1538 gpio0: gpio0@ff460000 { 1539 compatible = "rockchip,gpio-bank"; 1540 reg = <0xff460000 0x100>; 1541 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1542 clocks = <&pmucru PCLK_GPIO0>; 1543 1544 gpio-controller; 1545 #gpio-cells = <2>; 1546 1547 interrupt-controller; 1548 #interrupt-cells = <2>; 1549 }; 1550 1551 gpio1: gpio1@ff620000 { 1552 compatible = "rockchip,gpio-bank"; 1553 reg = <0xff620000 0x100>; 1554 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&cru PCLK_GPIO1>; 1556 1557 gpio-controller; 1558 #gpio-cells = <2>; 1559 1560 interrupt-controller; 1561 #interrupt-cells = <2>; 1562 }; 1563 1564 gpio2: gpio2@ff630000 { 1565 compatible = "rockchip,gpio-bank"; 1566 reg = <0xff630000 0x100>; 1567 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&cru PCLK_GPIO2>; 1569 1570 gpio-controller; 1571 #gpio-cells = <2>; 1572 1573 interrupt-controller; 1574 #interrupt-cells = <2>; 1575 }; 1576 1577 gpio3: gpio3@ff640000 { 1578 compatible = "rockchip,gpio-bank"; 1579 reg = <0xff640000 0x100>; 1580 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&cru PCLK_GPIO3>; 1582 1583 gpio-controller; 1584 #gpio-cells = <2>; 1585 1586 interrupt-controller; 1587 #interrupt-cells = <2>; 1588 }; 1589 1590 gpio4: gpio4@ff650000 { 1591 compatible = "rockchip,gpio-bank"; 1592 reg = <0xff650000 0x100>; 1593 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&cru PCLK_GPIO4>; 1595 1596 gpio-controller; 1597 #gpio-cells = <2>; 1598 1599 interrupt-controller; 1600 #interrupt-cells = <2>; 1601 }; 1602 }; 1603}; 1604 1605#include "rv1126-pinctrl.dtsi" 1606 1607
